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參數(shù)資料
| 型號： | FIN224ACGFX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER/DESERIALIZER 42BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 676Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 22 |
| 輸出數(shù)： | 22 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 42-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 42-BGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1217 (CN2011-ZH PDF) |
| 其它名稱： | FIN224ACGFXDKR |
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2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224AC Rev.1.1.6
13
Notes:
3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6. a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Control Logic Timing Controls
Note:
7. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
tPHL_DIR,
tPLH_DIR
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW
17
ns
tPLZ, tPHZ
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH
25
ns
tPZL, tPZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
25
ns
tPLZ, tPHZ
Deserializer Disable Time:
S0 or S1 to DP
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH,
Figure 14.
25
ns
tPZL, tPZH
Deserializer Enable Time:
S0 or S1 to DP
DIRI = 0,(7.)
S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 14.
2
s
tPLZ, tPHZ
Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW,
Figure 13.
25
ns
tPZL, tPZH
Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH,
Figure 13.
65
ns
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
CIN
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
2
pF
CIO
Capacitance of Parallel Port Pins
DP1:12
DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
2
pF
CIO-DIFF
Capacitance of Differential I/O
Signals
DIRI = 0, S1 = S2 = 0,
VDD = 2.775V
2
pF
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