參數(shù)資料
型號: FIN224ACGFX
廠商: Fairchild Semiconductor
文件頁數(shù): 17/19頁
文件大?。?/td> 0K
描述: IC SERIALIZER/DESERIALIZER 42BGA
標(biāo)準(zhǔn)包裝: 1
系列: SerDes™
功能: 串行器/解串器
數(shù)據(jù)速率: 676Mbps
輸入類型: LVCMOS
輸出類型: LVCMOS
輸入數(shù): 22
輸出數(shù): 22
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -30°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 42-VFBGA
供應(yīng)商設(shè)備封裝: 42-BGA
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1217 (CN2011-ZH PDF)
其它名稱: FIN224ACGFXDKR
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2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224AC Rev.1.1.6
7
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVC-
MOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
VDDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVC-
MOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidi-
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deseri-
alizer, unused data I/O can be treated as unused outputs.
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