參數(shù)資料
型號： FDW2507NZ
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 小信號晶體管
英文描述： Common Drain N-Channel 2.5V specified PowerTrench MOSFET
中文描述： 7500 mA, 20 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝： TSSOP-8
文件頁數(shù)： 2/5頁
文件大?。?/td> 130K
代理商： FDW2507NZ
FDW2507NZ Rev C2
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
V
GS
= 0 V,
I
D
= 250
μ
A
20
V
Breakdown Voltage Temperature
I
D
= 250
μ
A, Referenced to 25
°
C
–13
mV/
°
C
V
DS
= 16 V,
V
GS
= 12 V,
V
GS
= –12 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
1
10
–10
μ
A
μ
A
μ
A
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
,
I
D
= 250
μ
A, Referenced to 25
°
C
V
GS
= 4.5 V,
V
GS
= 2.5 V,
V
GS
= 4.5 V, I
D
= 7.5 A, T
J
=125
°
C
V
GS
= 4.5 V,
V
DS
= 5 V,
I
D
= 250
μ
A
0.6
0.8
1.5
V
Gate Threshold Voltage
4
mV/
°
C
I
D
= 7.5 A
I
D
= 6.8 A
15
17
20
19
23
27
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
V
DS
= 5 V
I
D
= 7.5 A
30
A
S
31
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
2152
512
263
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
12
13
35
19
20
3
5
22
23
56
34
28
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 7.5 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
Q
rr
Diode Reverse Recovery Charge
1.3
A
V
SD
V
GS
= 0 V,
I
S
= 1.3 A
(Note 2)
0.6
1.2
V
26
21
nS
nC
I
F
= 7.5A
d
iF
/d
t
= 100 A/μs
(Note 2)
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a)
77°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b)
114°C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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