參數(shù)資料
型號(hào)： FDU3706
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： JFETs
英文描述： 30V N-Channel PowerTrench MOSFET
中文描述： 14.7 A, 20 V, 0.009 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-251AA
封裝： IPAK-3
文件頁(yè)數(shù)： 2/5頁(yè)
文件大?。?/td> 113K
代理商： FDU3706
FDD3706/FDU3706 Rev C (W)
D
R
P
DS(ON)
Electrical Characteristics
Symbol
Drain-Source Avalanche Ratings
(Note 2)
E
AS
Drain-Source Avalanche Energy
I
AS
Drain-Source Avalanche Current
T
A
= 25°C unless otherwise noted
Test Conditions
Parameter
Min Typ Max Units
Single Pulse, V
DD
= 10V, I
D
=7A
60
7
mJ
A
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage V
GS
= 0 V,
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
I
D
= 250
μ
A
20
V
Breakdown Voltage Temperature
I
D
= 250
μ
A,Referenced to 25
°
C
13
mV/
°
C
V
DS
= 16 V,
V
GS
= 12 V,
V
GS
= –12 V
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
1
μ
A
nA
nA
100
–100
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
,
I
D
= 250
μ
A,Referenced to 25
°
C
V
GS
= 10 V,
V
GS
= 4.5 V,
V
GS
= 2.5 V,
V
GS
= 4.5 V, I
D
= 14.7 A,T
J
= 125
°
C
V
GS
= 4.5 V,
V
DS
= 5 V
V
DS
= 5 V,
I
D
= 14.7 A
I
D
= 250
μ
A
0.5
1
1.5
V
Gate Threshold Voltage
–3.5
mV/
°
C
I
D
= 16.2 A
I
D
= 14.7 A
I
D
= 12.2 A
7.5
8
11
12.6
65
9
11
16
19
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
30
A
S
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
1882
430
201
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
11
15
35
16
16
3.7
4
20
27
56
29
23
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10V,
V
GS
= 4.5 V
I
D
= 14.7 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward Voltage V
GS
= 0 V,
3.2
1.2
A
V
I
S
= 3.2 A
(Note 2)
0.7
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) R
θ
JA
= 40°C/W when mounted on a
1in
2
pad of 2 oz copper
b) R
JA
= 96°C/W when mounted
on a minimum pad.
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
Scale 1 : 1 on letter size paper
3.
Maximum current is calculated as:
where P
D
is maximum power dissipation at T
C
= 25°C and R
DS(on)
is at T
J(max)
and V
GS
= 10V. Package current limitation is 21A
F
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