參數(shù)資料
型號: FDS6679Z
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 小信號晶體管
英文描述: 30 Volt P-Channel PowerTrench MOSFET
中文描述: 13000 mA, 30 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: SO-8
文件頁數(shù): 2/5頁
文件大小: 66K
代理商: FDS6679Z
FDS6679Z Rev C(W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
V
GS
= 0 V,
I
D
= –250
μ
A
–30
V
Breakdown Voltage Temperature
I
D
= –250
μ
A,Referenced to 25
°
C
–22
mV/
°
C
V
DS
= –24 V, V
GS
= 0 V
V
GS
= –25 V, V
DS
= 0 V
V
GS
= 20 V, V
DS
= 0 V
–1
–10
10
μ
A
μ
A
μ
A
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= –250
μ
A
I
D
= –250
μ
A,Referenced to 25
°
C
V
GS
= –10 V, I
D
= –13 A
V
GS
= –4.5 V, I
D
= –11 A
V
GS
=–4.5 V, I
D
=–13A, T
J
=125
°
C
V
GS
= –4.5 V, V
DS
= –5 V
V
DS
= –5 V, I
D
= –13 A
–1
–1.7
–3
V
Gate Threshold Voltage
4.9
mV/
°
C
7.2
10
10
43
9
13
13
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
–50
A
S
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
3803
974
490
pF
pF
pF
V
DS
= –15 V, V
GS
= 0 V,
f = 1.0 MHz
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
18
9
92
54
67
11
15
32
18
147
86
94
ns
ns
ns
ns
nC
nC
nC
V
DD
= –15 V, I
D
= –1 A,
V
GS
= –10 V, R
GEN
= 6
V
DS
= –15 V, I
D
= –13 A,
V
GS
= –10 V
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
–2.1
A
V
SD
V
GS
= 0 V, I
S
= –2.1 A
(Note 2)
–0.7
–1.2
V
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 50°C/W (10 sec)
62.5°C/W steady state
when mounted on a
1in
2
pad of 2 oz
copper
b) 105°C/W when
mounted on a .04 in
2
pad of 2 oz copper
c) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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