參數(shù)資料
型號: FDN5618P
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: 60V P-Channel Logic Level PowerTrench MOSFET
中文描述: 60 V, P-CHANNEL, Si, POWER, MOSFET
封裝: SUPERSOT-3
文件頁數(shù): 2/8頁
文件大小: 385K
代理商: FDN5618P
FDN5618P Rev B(W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
===
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
V
GS
= 0 V, I
D
= –250
μ
A
I
D
= –250
μ
A,Referenced to 25
°
C
-60
V
Breakdown Voltage Temperature
–58
mV/
°
C
V
DS
= –48 V,
V
GS
= 20V,
V
GS
= –20 V
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
–1
100
–100
μ
A
nA
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
===
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= –250
μ
A
I
D
= –250
μ
A,Referenced to 25
°
C
–1
–1.6
4
–3
V
Gate Threshold Voltage
mV/
°
C
V
GS
= –10 V,
V
GS
= –4.5 V,
V
GS
= –10 V, I
D
= –3 A T
J
=125
°
C
V
GS
= –10 V,
V
DS
= –5 V,
I
D
= –1.25 A
I
D
= –1.0 A
0.148
0.185
0.245
0.170
0.230
0.315
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
V
DS
= –5 V
I
D
= –1.25 A
–5
A
S
4.3
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
430
52
19
pF
pF
pF
V
DS
= –30 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
6.5
8
16.5
4
8.6
1.5
1.3
13
16
30
8
13.8
ns
ns
ns
ns
nC
nC
nC
V
DD
= –30 V,
V
GS
= –10 V,
I
D
= –1 A,
R
GEN
= 6
V
DS
= –30 V,
V
GS
= –10 V
I
D
= –1.25 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
–0.42
–1.2
A
V
V
GS
= 0 V,
I
S
= –0.42
(Note 2)
–0.7
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 250
°
C/W when mounted on a
0.02 in
2
pad of 2 oz. copper.
b) 270°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width
=
300
μ
s, Duty Cycle
=
2.0
F
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