參數(shù)資料
型號: FDG6331L
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: Integrated Load Switch
中文描述: BUF OR INV BASED PRPHL DRVR, PDSO6
封裝: SC-70, SMT-6
文件頁數(shù): 2/4頁
文件大?。?/td> 54K
代理商: FDG6331L
FDG6331L Rev B (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min
Typ
Max Units
Off Characteristics
BV
IN
Vin Breakdown Voltage
I
Load
Zero Gate Voltage Drain Current
I
FL
Leakage Current, Forward
I
RL
Leakage Current, Reverse
V
ON/OFF
= 0 V, I
D
= –250
μ
A
V
IN
= –6.4 V,
V
ON/OFF
= 0 V, V
IN
= 8 V
V
ON/OFF
= 0 V, V
IN
= –8 V
8
V
μ
A
nA
nA
V
ON/OFF
= 0 V
–1
100
–100
On Characteristics
V
ON/OFF (th)
Gate Threshold Voltage
R
DS(on)
Static Drain–Source
On–Resistance (Q2)
(Note 2)
V
IN
= V
ON/OFF
, I
D
= –250
μ
A
V
IN
= 4.5 V,
V
IN
=2.5 V,
V
IN
= 1.8 V,
V
IN
= 4.5 V,
V
IN
= 2.7 V,
0.4
0.9
155
193
248
310
380
1.5
260
330
450
400
500
V
I
D
= –0.8 A
I
D
= –0.7 A
I
D
= –0.6 A
I
D
= 0.4A
I
D
= 0.2 A
m
m
R
DS(on)
Static Drain–Source
On–Resistance (Q1)
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
–0.25
–1.2
A
V
V
ON/OFF
= 0 V, I
S
= –0.25 A
(Note 2)
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
JA
is determined by the user’s board design.
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%.
FDG6331L Load Switch Application Circuit
Q2
Q1
R1
IN
OUT
ON/OFF
LOAD
C1
R2
External Component Recommendation:
For additional in-rush current control, R2 and C1 can be added. For more information, see application note AN1030.
F
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