參數(shù)資料
型號： FDG6324L
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： Integrated Load Switch
中文描述： 0.27 A BUF OR INV BASED PRPHL DRVR, PDSO6
封裝： SC-70, 6 PIN
文件頁數(shù)： 2/7頁
文件大?。?/td> 173K
代理商： FDG6324L
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
I
FL
ON CHARACTERISTICS
(Note 3)
Forward Leakage Current
V
IN
= 20 V, V
ON/OFF
= 0 V
1
μA
V
DROP
Conduction Voltage Drop
V
IN
= 12 V, V
ON/OFF
= 3.3 V, I
L
= 0.36 A
0.14
0.2
V
V
IN
= 5 V, V
ON/OFF
= 3.3 V, I
L
= 0.27 A
0.16
0.2
R
(ON)
Q
2
- Static On-Resistance
V
GS
= -12 V, I
D
= -0.6 A
0.37
0.55
V
GS
= -5 V, I
D
= -0.5 A
0.58
0.75
I
L
Load Current
V
DROP
= 0.2 V, V
IN
= 12 V, V
ON/OFF
= 3.3 V
0.36
A
V
DROP
= 0.2 V, V
IN
= 5 V, V
ON/OFF
= 3.3 V
0.27
Notes:
1. Range of V
in
can be up to 25V, but R
1
and R
2
must be scaled such that V
GS
of Q2 does not exceed -20V.
2. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is
guaranteed by design while R
θ
CA
is determined by the user's board design. Thermal ratings based on minimum mounting pad.
3. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%
FDG6324L Load Switch Application
External Component Recommendation
For Co
≤
1uF applications:
R1 is required to turn Q2 off.
R2 and C1 are optional for slew rate control.
First select R2, 100 -1K
, for slew rate control.
Then select R1 such that the ratio R1/R2 is maintained between 10-100.
SPICE model (FDG6324L.MOD) available at www.fairchildsemi.com.
FDG6324L Rev.D
APPLICATION CIRCUIT
IN
OUT
C1
LOAD
Q2
R1
R2
ON/OFF
Q1
Co
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