參數(shù)資料
型號(hào): FBL22041BB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 3.3V BTL 7-bit Futurebus transceiver standard A-port
中文描述: FBL SERIES, 7-BIT TRANSCEIVER, INVERTED OUTPUT, PQFP52
文件頁(yè)數(shù): 3/14頁(yè)
文件大?。?/td> 93K
代理商: FBL22041BB
Philips Semiconductors
Product specification
FBL22041
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
1998 Aug 12
3
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19
20
21 22 23 24 25 26
V
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
N/C
LOGIC GND
AI1
AI2
AO2
LOGIC GND
AO3
LOGIC GND
AI3
AI4
AO4
LOGIC GND
AO5
LOGIC GND
A
L
A
B
T
T
A
O
B
A
A
O
T
T
B
O
B
B
V
V
O
7-Bit Transceiver
52-lead PQFP
A
O
O
O
SG00084
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when V
CC
is below 1.3V.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
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