參數(shù)資料
型號: FBL22031BB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver with 30W termination
中文描述: FBL SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 7/16頁
文件大小: 168K
代理商: FBL22031BB
Philips Semiconductors
Product specification
FBL22031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver with 30
termination
2000 Apr 18
7
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
–0.5 to +4.6
V
V
IN
Input voltage
AI0 – AI6, OEB0, OEBn, OEAn
–0.5 to +7.0
V
B0 – B8
–0.5 to +3.5
V
I
IN
Input current
V
IN
0
–50
V
V
OUT
Voltage applied to output in High output state
–0.5 to +7.0
V
I
OUT
Current applied to output in
Low output state/High output state
AO0 – AO8
24, –24
mA
B0 – B8
200
mA
°
C
T
STG
Storage temperature
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
COMMERCIAL LIMITS
V
CC
= 3.3V
±
10%;
T
amb
= –40 to +85
°
C
MIN
TYP
3.0
3.3
UNIT
MAX
3.6
V
CC
Supply voltage
V
V
IH
High level input voltage
High-level input voltage
Except B0–B8
2.0
V
B0 – B8
1.62
1.55
V
V
IL
Low level input voltage
Low-level input voltage
Except B0–B8
0.8
V
B0 – B8
1.47
V
I
IK
I
OH
Input clamp current
–18
mA
High-level output current
AO0 – AO8
–12
mA
I
OL
Low level output current
Low-level output current
AO0 – AO8
+12
mA
B0 – B8
100
mA
C
OB
T
amb
Output capacitance on B port
6
7
pF
°
C
Operating free-air temperature range
0
+70
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
TYP
MAX
V
BIASV
Bias pin voltage
Voltage difference between the Bias voltage
and V
CC
after the PCB is plugged in.
V
CC
= 0 V, Bias V = 3.6V
V
CC
= 3.3V, Bias V = 3.6V
B0 – B8 = 0V, Bias V = 3.3V
0.5
V
I
BIASV
Bias pin (I
) input DC
BIASV
current
1.2
mA
μ
A
V
μ
A
μ
A
10
V
Bn
I
LM
I
HM
Bus voltage during prebias
1.62
2.1
Fall current during prebias
B0 – B8 = 2V, Bias V = 1.3 to 2.5V
1
Rise current during prebias
B0 – B8 = 1V, Bias V = 3 to 3.6V
-1
I
Bn
PEAK
Peak bus current during
insertion
V
CC
= 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, t
r
= 2ns
V
CC
= 0 to 3.3V, OEB0 = 0.8V
V
CC
= 0 to 1.2V, OEB0 = 0 to 5V
V
CC
= 3.3V
10
mA
I
OL
OFF
Power up current
100
μ
A
100
t
GR
Input glitch rejection
1.0
1.35
ns
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