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參數(shù)資料
| 型號(hào)： | FAN8035L |
| 英文描述： | MOTOR CONTROLLER |
| 中文描述： | 電機(jī)控制器 |
| 文件頁數(shù)： | 64/191頁 |
| 文件大?。?/td> | 2018K |
| 代理商： | FAN8035L |
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FAN5061
12
P
Application Circuit Summary
Table 4 summarizes the worst-case design schematics presented in this section. The basic choices are: A) The processor, B) the
chipset used, and C) the use or not of a sense resistor. Depending on board layout and component selection, it may be possible to
use fewer output capacitors than shown here. For configurations not shown in this datasheet, consult the Appendix for selection
of component values.
Table 4. Recommended Values for CPU-based Applications
*Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details.
See the Appendix to this datasheet for the method of calculation of these components. Pin 4 must be used to remote sense the
voltage at the processor to achieve the specified performance.
Processor
Coppermine
Katmai
Mendocino
Katmai
Chipset
Whitney
Camino
Whitney
BX
C
IN
3
4
4
5
C
OUT
*
4
6
5
6
R5, R7 (K
)
8.45
13.0
11.3
11.8
Test Parameters
Figure 3. Ouput Drive Timing Diagram
Application Information
The FAN5061 Controller
The FAN5061 is a programmable synchronous DC-DC con-
troller IC. When designed around the appropriate external
components, the FAN5061 can be configured to deliver more
than 16A of output current, as appropriate for the Katmai and
Coppermine and other processors. The FAN5061 functions
as a fixed frequency PWM step down regulator.
Main Control Loop
Refer to the FAN5061 Block Diagram on page 1. The FAN5061
implements “summing mode control”, which is different from
both classical voltage-mode and current-mode control. It
provides superior performance to either by allowing a large
converter bandwidth over a wide range of output loads.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers feeding
into a comparator which provides the input to the digital control
block. The signal conditioning section accepts input from the
DROOP (current feedback) and VFB (voltage feedback) pins
and sets up two controlling signal paths. The first, the voltage
control path, amplifies the difference between the VFB signal
and the reference voltage from the DAC and presents the
output to one of the summing amplifier inputs. The second,
current control path, takes the difference between the DROOP
and SW pins when the high-side MOSFET is on, reproducing
the voltage across the MOSFET and thus the input current; it
presents the resulting signal to another input of the summing
amplifier. These two signals are then summed together. This
output is then presented to a comparator looking at the oscillator
ramp, which provides the main PWM control signal to the
digital control block.
The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.
There is an additional comparator in the analog control section
whose function is to set the point at which the FAN5061 cur-
rent limit comparator disables the output drive signals to the
external power MOSFETs.
High Current Output Drivers
The FAN5061 contains two identical high current output driv-
ers that utilize high speed bipolar transistors in a push-pull
configuration. The drivers’ power and ground are separated
from the chip’s power and ground for switching noise immu-
nity. The power supply pin, VCCP, is supplied from an exter-
nal 12V source through a series 33
resistor. The resulting
voltage is sufficient to provide the gate to source drive to the
external MOSFETs required in order to achieve a low R
DS,ON
.
Internal Voltage Reference
The reference included in the FAN5061 is a precision band-gap
voltage reference. Its internal resistors are precisely trimmed
to provide a near zero temperature coefficient (TC). Based on
the reference is the output from an integrated 5-bit DAC. The
DAC monitors the 5 voltage identification pins, VID0-4. When
the VID4 pin is at logic HIGH, the DAC scales the reference
voltage from 2.0V to 3.5V in 100mV increments. When VID4
t
R
5V
t
DT
t
DT
t
F
HIDRV
to SW
LODRV
2V
2V
2V
5V
2V
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