參數(shù)資料
型號： FAN6920MRMY
廠商： Fairchild Semiconductor
文件頁數(shù)： 19/24頁
文件大?。?/td> 1490K
描述： IC PWM CTLR PFC/QUASI-RES 16SOP
標(biāo)準(zhǔn)包裝： 1
模式： 臨界傳導(dǎo)（CRM）
電流 - 啟動： 20µA
電源電壓： 12 V ~ 25 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： FAN6920MRMYDKR
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6920MR " Rev. 1.0.8
19
 
PFC Burst Mode
To   minimize   the   power   dissipation   at   light-load
condition, the FAN6920MR PFC control enters burst-
mode operation. As the load decreases, the PWM
feedback voltage (V
FB
) decreases. When V
FB
  < V
CTRL-
PFC-BM
  for 100 ms, the device enters PFC burst mode,
the V
COMP
 pulls high to V
COMP-H
, and PFC output voltage
increases. When the PFC feedback voltage on INV pin
(V
INV
) triggers the OVP threshold voltage (V
INV-OVP
),
V
COMP
  pulls low to V
COMP-L
, the OPFC pin switching
stops and the PFC output voltages start to drop. Once
the V
INV
 drops below the feedback comparator reference
voltage (V
REF
), V
COMP
  pulls high to V
COMP-H
  and OPFC
starts switching again. Burst-mode operation alternately
enables and disables switching of the power MOSFET
to reduce the switching loss at light-load condition.
P F C B urst M ode
V
CO M P -H
V
CO M P
E nter P F C B urst M ode
O PFC
V
INV
V
C O M P -L
N orm al
M
V
IN V -O V P
V
R E F
 
Figure 36. PFC Burst Mode Behavior
The V
COMP-H
is adjusted by the VIN pin voltage, as
shown in Figure 37. Since the VIN pin is connected to
rectified AC input line voltage through the resistive
divider, a higher line voltage generates a higher VIN pin
voltage. The V
COMP-H
decreases as VIN pin voltage
increases, limiting the PFC choke current at a higher
input voltage to reduce acoustic noise. If the V
COMP-H
is
below the PFC V
OZ
, the PFC automatically shuts down
at light load with high line voltage input condition.
 
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
1.2
1.7
2.2
2.7
3.2
3.7
4.2
V
V IN
(V )
V
OZ
 
Figure 37. V
COMP-H
 Voltage vs. V
VIN
 Voltage
Characteristic Curve
PWM Stage
HV Startup and Operating Current (HV Pin)
The HV pin is connected to the AC line through a
resistor (refer to  Figure 1). With a built-in high-voltage
startup circuit, when AC voltage is applied to the power
system, FAN6920MR provides a high current to charge
the external V
DD
  capacitor to speed up controllers
startup time and build up normal rated output voltage
within three seconds. To save power consumption, after
V
DD
 voltage exceeds turn-on voltage and enters normal
operation; this high-voltage startup circuit is shut down
to avoid power loss from startup resistor.
Figure 38 shows the characteristic curve of V
DD
 voltage
and operating current I
DD
. When V
DD
  voltage is lower
than   V
DD-PWM-OFF
,   FAN6920MR   stops   all   switching
operation and turns off unnecessary internal circuits to
reduce operating current. By doing so, the period from
V
DD-PWM-OFF
 to V
DD-OFF
 can be extended and the hiccup
mode frequency can be decreased to reduce the input
power in case of output short circuit. Figure 39 shows
the typical waveforms of V
DD
  voltage and gate signal
with hiccup mode operation.
I
DD-OP
I
DD-PWM-OFF
I
DD-ST
V
DD
V
DD-OFF
V
DD-ON
V
DD-PWM-OFF
I
DD
 
Figure 38. V
DD
 vs. I
DD-OP
 Characteristic Curve
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FAN6921ML 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller
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