?2010 Fairchild Semiconductor Corporation 
 
www.fairchildsemi.com 
FAN6920MR  "  Rev. 1.0.8 
17 
 
RANGE Pin 
A built-in low-voltage MOSFET can be turned on or off 
according  to  V
VIN
  voltage  level  and  PFC  status.  The 
drain  pin  of  this  internal  MOSFET  is  connected  to  the 
RANGE pin. Figure 29 shows the status curve of V
VIN
 
voltage level and RANGE impedance (open or ground).  
V
VIN
RANGE=
Ground
V
VIN-RANGE-L
V
VIN-RANGE-H
RANGE=
Open
PFC Normal Mode Condition
PFC Burst Mode Condition
 
Figure 29. Hysteresis Behavior between RANGE Pin 
and VIN Pin Voltage 
Zero-Current Detection (ZCD Pin) 
Figure  30  shows  the  internal  block  of  zero-current 
detection.   The   detection   function   is   performed   by 
sensing  the  information  on  an  auxiliary  winding  of  the 
PFC inductor. Referring to Figure 31, when PFC MOS is 
off,  the  stored  energy  of  the  PFC  inductor  starts  to 
release  to  the  output  load.  Then  the  drain  voltage  of 
PFC  MOS  starts  to  decrease  since  the  PFC  inductor 
resonates with parasitic capacitance. Once the ZCD pin 
voltage  is  lower  than  the  triggering  voltage  (1.75 V 
typical), the PFC gate signal is sent again to start a new 
switching cycle. 
If  PFC  operation  needs  to  be  shut  down  due  to 
abnormal  condition,  pull  the  ZCD  pin  LOW,  voltage 
under   0.2 V   (typical),   to   activate   the   PFC   disable 
function to stop PFC switching operation. 
For  preventing  excessive  high  switching  frequency  at 
light  load,  a  built-in  inhibit  timer  is  used  to  limit  the 
minimum  t
OFF
  time.  Even  if  the  ZCD  signal  has  been 
detected,  the  PFC  gate  signal  is  not  sent  during  the 
inhibit time (2.5 祍 typical). 
5
1 0 V
1 .7 5 V
Z C D
FA N 6 9 2 0 M R
1 :n
V
AC
L
b
0 .2 5 V
PF C  G a te  O n
2 .1 V
R
S
Q
P F C  G a te  
D riv e
R
S
Q
R
Z C D
0 .2 V
 
Figure 30. Internal Block of the Zero-Current 
Detection 
V
ZCD
PFC 
G ate
V
IN,M AX
PFCVO
V
DS
10V
2.1V
1.75V
Inhibit 
Tim e
t
t
t
 
Figure 31. Operation Waveforms of PFC 
Zero-Current Detection 
Protection for PFC Stage 
PFC Output Voltage UVP and OVP (INV Pin) 
FAN6920MR  provides  several  kinds  of  protection  for 
PFC  stage.  PFC  output  over-  and  under-voltage  are 
essential   for   PFC   stage.   Both   are   detected   and 
determined by INV pin voltage, as shown in Figure 32. 
When  INV  pin  voltage is over 2.75 V  or under  0.45 V, 
due to overshoot or abnormal conditions, and lasts for a 
de-bounce time around 70 祍; the OVP or UVP circuit is 
activated to stop PFC switching operation immediately. 
The  INV  pin  is  not  only  used  to  receive  and  regulate 
PFC  output  voltage;  it  can  also  perform  PFC  output 
OVP/ UVP protection. For failure-mode test, this pin can 
shut down PFC switching if pin floating occurs. 
3
2
V
c o m  p
E r r o r
A m  p lif ie r
C O M P
F A N 6 9 2 0 M R
O V P  =  (V
IN V
 e  2 .7 5 V )
U V P  =  (V
I N V
 d  0 .4 5 V )
V o lt a g e  
D e t e c t o r
IN V
C
O
V
O
D e b o u n c e
T im  e
D r iv e r
V
R  E  F
  ( 2 . 5 V )
c o m p
 
Figure 32. Internal Block of PFC Over- 
and Under-Voltage Protection