參數(shù)資料
      型號(hào): FAN4800ASNY
      廠商: Fairchild Semiconductor
      文件頁(yè)數(shù): 15/19頁(yè)
      文件大?。?/td> 860K
      描述: IC CTLR COMBO PFC/PWM 16-DIP
      標(biāo)準(zhǔn)包裝: 30
      模式: 平均電流
      頻率 - 開(kāi)關(guān): 240kHz ~ 268kHz
      電流 - 啟動(dòng): 30µA
      電源電壓: 11 V ~ 26 V
      工作溫度: -40°C ~ 105°C
      安裝類(lèi)型: 通孔
      封裝/外殼: 16-DIP(0.300",7.62mm)
      供應(yīng)商設(shè)備封裝: 16-DIP
      包裝: 管件
       
      ?2010 Fairchild Semiconductor Corporation
       
      www.fairchildsemi.com
      FAN4800AS/CS/01S/02S " Rev. 1.0.2
      15
       
      Two-Level PFC Function
      To improve the efficiency, the system can reduce PFC
      switching loss at low line and light load by reducing the
      PFC output voltage. The two-level PFC output of the
      FAN4801S/02S can be programmable.
      As Figure 27 shows, FAN4801S/02S detect the voltage
      of VEA and VRMS pins to determine if the system
      operates low line and light load. At the second-level
      PFC, there is a current of 20 礎(chǔ) through R
      F2
       from the
      FBPFC pin. The second-level PFC output voltage can
      be calculated as.
      (
      )
      1   2
      2
      2
      2.5
      20
      F    F
      F
      F
      R    R
      Output
      V
      A   R
      R
      ?/DIV>
      +
      E
      ?/DIV>
      
      ?/DIV>
       
      (3)
      For example, if the second-level PFC output voltage is
      expected   as   300 V   and   normal   voltage   is   387 V,
      according to the equation, R
      F2
       is 28 k& R
      F1
       is 4.3 M&.
      The programmable range of second level PFC output
      voltage is 340 V ~ 300 V.
       
      Figure 27.    Two-Level PFC Scheme
      Oscillator (RT/CT)
      The oscillator frequency is determined by the values of
      R
      T
        and C
      T
      , which determine the ramp and off-time of
      the oscillator output clock:
      /
      /
      1
      RT  CT
      RT  CT    DEAD
      f
      t
      t
      =
      +
       
      (4)
      The dead time of the oscillator is derived from the
      following equation:
      /
      1
      ln
      3.8
      RT  CT
      T
      T
      VREF
      t
      C    R
      VREF
      
      ?/DIV>
      ?/DIV>
      =
      ?/DIV>
      ?/DIV>
      ?/DIV>
      ?/DIV>
      
      ?/DIV>
      ?/DIV>
       
      (5)
      at V
      REF
      =7.5 V and t
      RT/CT
      =C
      T
       x R
      T
       x 0.56.
      The dead time of the oscillator is determined using:
      2.8
      360
      7.78
      DEAD
      T
      T
      V
      t
      C
      C
      mA
      =
      ?/DIV>
      =
      ?/DIV>
       
      (6)
      The dead time is so small (t
      RT/CT
      >>t
      DEAD
      ) that the
      operating frequency can typically be approximated by:
      /
      /
      1
      RT  CT
      RT  CT
      f
      t
      =
       
      (7)
       
      Pulse Width Modulator (PWM)
      The operation of the PWM section is straightforward,
      but there are several points that should be noted.
      Foremost among these is the inherent synchronization
      of PWM with the PFC section of the device, from which
      it also derives its basic timing. The PWM is capable of
      current-mode or voltage-mode operation. In current-
      mode applications, the PWM ramp (RAMP) is usually
      derived   directly   from   a   current-sensing   resistor   or
      current transformer in the primary side of the output
      stage. It is thereby representative of the current flowing
      in the converters output stage. I
      LIMIT
      , which provides
      cycle-by-cycle current limiting, is typically connected to
      RAMP in such applications. For voltage-mode operation
      and certain specialized applications, RAMP can be
      connected to a separate RC timing network to generate
      a voltage ramp against which FBPWM is compared.
      Under these conditions, the use of voltage feedforward
      from the PFC bus can assist in line regulation accuracy
      and response. As in current-mode operation, the I
      LIMIT
       
      input is used for output stage over-current protection.
      No voltage error amplifier is included in the PWM stage,
      as this function is generally performed on the output
      side of the PWMs isolation boundary. To facilitate the
      design of opto-coupler feedback circuitry, an offset has
      been built into the PWMs RAMP input that allows
      FBPWM to command a 0% duty cycle for input voltages
      below typical 1.5 V.
      PWM Cycle-by-Cycle Current Limiter
      The ILIMIT pin is a direct input to the cycle-by-cycle
      current limiter for the PWM section. Should the input
      voltage at this pin exceed 1 V, the output flip-flop is reset
      by the clock pulse at the start of the next PWM power
      cycle. When the I
      LIMIT
       triggers the cycle-by-cycle bi-cycle
      current, it limits the PWM duty cycle mode and the power
      dissipation is reduced during the dead-short condition.
      V
      IN
       OK Comparator
      The V
      IN
        OK comparator monitors the DC output of the
      PFC and inhibits the PWM if the voltage on FBPFC is
      less than its nominal 2.4 V. Once the voltage reaches
      2.4 V, which corresponds to the PFC output capacitor
      being charged to its rated boost voltage, soft-start begins.
      PWM Soft-Start (SS)
      PWM startup is controlled by selection of the external
      capacitor   at   soft-start.   A   current   source   of   10 礎(chǔ)
      supplies the charging current for the capacitor and
      startup of the PWM begins at 1.5 V.
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