參數(shù)資料
型號: FAN4800ASNY
廠商: Fairchild Semiconductor
文件頁數(shù): 14/19頁
文件大?。?/td> 860K
描述: IC CTLR COMBO PFC/PWM 16-DIP
標(biāo)準(zhǔn)包裝: 30
模式: 平均電流
頻率 - 開關(guān): 240kHz ~ 268kHz
電流 - 啟動: 30µA
電源電壓: 11 V ~ 26 V
工作溫度: -40°C ~ 105°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-DIP
包裝: 管件
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN4800AS/CS/01S/02S " Rev. 1.0.2
14
 
TriFault Detect"
To   improve   power   supply   reliability,   reduce   system
component count, and simplify compliance to UL1950
safety standards; the FAN4800AS/CS/01S/02S includes
TriFault   Detect"   technology.   This   feature   monitors
FBPFC for certain PFC fault conditions.
In a feedback path failure, the output of the PFC could
exceed safe operating limits. With such a failure, FBPFC
exceeds its normal operating area. Should FBPFC go too
low, too high, or open; TriFault Detect" senses the error
and terminates the PFC output drive.
TriFault Detect is an entirely internal circuit. It requires no
external components to serve its protective function. 
PFC Over-Voltage Protection
In    the    FAN4800AS/CS/01S/02S,    the    PFC    OVP
comparator serves to protect the power circuit from being
subjected to excessive voltages if the load changes
suddenly. A resistor divider from the high-voltage DC
output of the PFC is fed to FBPFC. When the voltage on
FBPFC exceeds 2.75 V, the PFC output driver is shut
down. The PWM section continues to operate. The OVP
comparator has 250 mV of hysteresis and the PFC does
not restart until the voltage at FBPFC drops below 2.5 V.
V
DD
  OVP can also serve as a redundant PFC OVP
protection. V
DD
 OVP threshold is 28 V with 1 V hysteresis.
Selecting PFC R
sense
 
R
sense
 is the sensing resistor of the PFC boost converter.
During the steady state, line input current x R
sense
 equals
I
GAINMOD
 x 5.7 k&.
At full load, the average V
VEA
 needs to around 4.5 V and
ripple on the VEA pin needs to be less than 400 mV.
Choose the resistance of the sensing resistor:
(
)
(
)
4.5   0.7    5.7
2
2    5.6   0.7
_
_
IN
SENSE
K   IAC   Gain  V
R
Line  Input   Power

?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
?/DIV>

?/DIV>
     (2)
where 5.6 is V
VEA
 maximum output voltage.
PFC Soft-Start
PFC startup is controlled by V
VEA
  level. Before the
FBPFC voltage reaches 2.4 V, the V
VEA
  level is around
2.8 V. At 90 V
AC
, the PFC soft-start time is 90 ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The PFC is disabled as AC input lowers, causing V
RMS
 to
be less than 1.05 V.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor because an increase in the input voltage
to the PWM causes a decrease in the input current. This
response dictates the proper compensation of the two
transconductance error amplifiers. Figure 26 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current-loop compensation
is returned to VREF to produce a soft-start characteristic
on the PFC. As the reference voltage increases from 0V,
it creates a differentiated voltage on IEA, which prevents
the PFC from immediately demanding a full duty cycle on
its boost converter. Complete design is discussed in
application note AN-6078SC.
There is an RC filter between R
sense
  and ISENSE pin.
There are two reasons to add a filter at the ISENSE pin:
1. Protection: During startup or inrush current conditions,
there is a large voltage across R
sense
, the sensing
resistor of the PFC boost converter. It requires the
I
SENSE
 filter to attenuate the energy.
2. To reduce inductance, L, the boost inductor. The
I
SENSE
 filter also can reduce the boost inductor value
since the I
SENSE
 filter behaves like an integrator before
the ISENSE pin, which is the input of the current error
amplifier, IEA.
The I
SENSE
 filter is an RC filter. The resistor value of the
I
SENSE
 filter is between 100 & and 50 & because I
OFFSET
 x
R
FILTER
  can generate a negative offset voltage of IEA.
Selecting an R
FILTER
 equal to 50 & keeps the offset of the
IEA less than 3 mV. Design the pole of the I
SENSE
 filter at
f
PFC
/6, one sixth of the PFC switching frequency, so the
boost   inductor   can   be   reduced   six   times   without
disturbing the stability. The capacitor of the I
SENSE
 filter,
C
FILTER
, is approximately 100 nF.
 
Figure 26. Compensation Network Connection for
the Voltage and Current Error Amplifiers
 
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