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參數(shù)資料
| 型號： | FA5305APS |
| 廠商： | FUJI ELECTRIC HOLDINGS CO., LTD. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Bipolar IC For Switching Power Supply Control |
| 中文描述： | 雙極集成電路開關(guān)電源控制 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 280K |
| 代理商： | FA5305APS |
FA5304AP(S)/FA5305AP(S)
10
I
Design advice
1. Startup circuit
It is necessary to start-up IC that the voltage inclination of VCC
terminal “dVcc/dt” satisfies the following equation(4).
dVcc/dt(V/s)>1.8/(Cs(
μ
F)).................................(4)
Cs : capacitor connected between CS terminal and GND
Note that equation (4) must be satisfied in any condition. Also,
it is necessary to keep “l(fā)atch mode” for overload protection or
overvoltage protection that the current supplied to VCC
terminal through startup resistor satisfies the following
equation(5).
Icc(Lat)>0.4mA for Vcc
Icc(Lat): Cutoff-state(=Latch mode) supply current
9.2V.......................(5)
The detail is explained as follows.
(1) Startup circuit connected to AC line directly
Fig. 20 shows a typical startup circuit that a startup resistor Rc
is connected to AC line directly. The period from power-on to
startup is determined by Rc, R
D
and C
A
. Rc, R
D
and C
A
must
be designed to satisfy the following equations.
dVcc/dt(V/s)=
(1/C
A
) {(V
AVE
–Vccon )/R
C
–Vccon/R
D
–Iccst} >
1.8/(Cs(
μ
F)).....................................................(6)
Rc(k
)< (V
AVE
–9.2(V))/{0.4 (mA) + (9.2(V)/R
D
(k
) } ...........(7)
V
AVE
= Vac
E
2/
π
: Average voltage applied to AC line side of Rc
Vac:
AC input effective voltage
Vccon: ON threshold of UVLO, 16.5V(max.)
Iccst:
Standby current, 0.15 mA(max.)
In this method, Vcc voltage includes ripple voltage influenced
by AC voltage. Therefore, enough dVcc/dt required by
equation (6) tend to be achieved easily when Vcc reaches to
Vccon even if Vcc goes up very slowly.
After power-off, Vcc does not rise up because a voltage
applied from bias winding to VCC terminal decreases and the
current flowing R
C
becomes zero, therefore, re-startup does
not occur after Vcc falls down below OFF threshold of UVLO
until next power-on.
Fig. 20 Startup circuit example(1)
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