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參數(shù)資料
| 型號： | FA3686V |
| 英文描述： | SMPS Controller |
| 中文描述： | 開關(guān)電源控制器 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 389K |
| 代理商： | FA3686V |
FA3686V
14
7. Timer latch short-circuit protection circuit
This IC has the timer latch short-circuit protection circuit. The
circuit cuts off the output of all channels when the output
voltage of DC-to-DC converter drops due to short circuit or
overload. Delay time of the timer latch mode is set by a counter
system in the internal circuit, therefore, no external parts are
necessary. When one of the output voltage of the DC-to-DC
converter drops due to a short circuit or overload, the FB1 and
FB3 pin voltage increases up to around the V
REG
voltage for
ch1 and ch3, or the FB2 pin voltage drops down to around 0V
for ch2.
The counter system operates when the FB1 or FB3 pin voltage
exceeds the timer latch threshold voltage of 2.0V(max.) or FB2
pin voltage falls below timer latch threshold voltage of
0.2V(min.). The counter system counts oscillator waveform. If
this system counts the oscillation cycles of 2
16
times (TL pin:
GND, 16th stage counter) or 2
17
times (TL pin: VREG, 17th
stage counter), this circuit detects short circuit. Then the IC is
set to off latch mode and the output of all channels is shut off
and the current consumption becomes 2.5mA (typ.). (Fig. 7)
If the DC-to-DC converters return to normal before counter
system counts 2
16
or 2
17
, counter is reset.
The period (tp) between the occurrences of short-circuit in the
converter output and setting to off latch mode can be calculated
by the following equations:
Example. When fosc=500kHz and TL pin to GND, the period tp is:
tp=2
16
1/500kHz=0.131sec.
You can reset off latched mode of the short-circuit protection by
either of the following ways to 1) CS pins, or 2) VCC pin:
1) Set the CS pin of the cause of off latch mode as follows.
CS1 pin voltage = 0V, CS2 pin voltage = VREG
2) V
CC
voltage is below UVLO off threshold voltage (2.1V typ.).
Connect the TL pin to either VREG or GND. If TL pin is
opened, the counter operation is unstable.
8. Output circuit
The IC contains a push-pull output stage and can directly drive
MOSFETs. The maximum peak current of the output stage is
sink current of +150mA, and source current of
–
400mA. The IC
can also drive NPN and PNP transistors. The maximum current
in such cases is ±50mA. You must design the output current
considering the rating of power dissipation. (See
“
Design
advice
”
.)
9. Undervoltage lockout circuit
The IC contains an undervoltage lockout circuit to protect the
circuit from the damage caused by malfunctions when the
supply voltage drops. When the supply voltage rises from 0V,
the IC starts to operate at V
CC
of 2.2V (typ.) and outputs
generate pulses. If a drop of the supply voltage occurs, it stops
output at V
CC
of 2.1V (typ.). When it occurs, the CS1 pin is
turned to low level and the CS2 pin to high level, and then these
pins are reset.
Timer latch count
Timer latch count
Momentary
short circuit
Short circuit
Short circuit
protection
tp
FB1 or 3
Time t
Time t
Off latch mode
Oscillator output
OUT1
Timer latch
count
Timer latch
count
Momentary
short circuit
Short circuit
Short circuit
protection
tp
FB2
Time t
Time t
Off latch mode
OUT2
Oscillation output
Fig. 7
Ch1
Ch2
tp [s] = 2
16
1
fosc
TL pin: GND
tp [s] = 2
17
1
fosc
TL pin: VREG
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