1-30 Revision 10 Table 1-20 eX Family Timing Characteristics (Worst-Case Commerc" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EX64-PTQ64I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 28/48闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA ANTIFUSE 3K 64-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� EX
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 128
杓稿叆/杓稿嚭鏁�(sh霉)锛� 41
闁€鏁�(sh霉)锛� 3000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 64-TQFP锛�10x10锛�
eX FPGA Architecture and Characteristics
1-30
Revision 10
Table 1-20 eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3 V, TJ = 70掳C)
鈥揚 Speed
Std Speed
鈥揊 Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
2.5 V LVCMOS Output Module Timing1 (VCCI = 2.3 V)
tDLH
Data-to-Pad LOW to HIGH
3.3
4.7
6.6
ns
tDHL
Data-to-Pad HIGH to LOW
3.5
5.0
7.0
ns
tDHLS
Data-to-Pad HIGH to LOW鈥擫ow Slew
11.6
16.6
23.2
ns
tENZL
Enable-to-Pad, Z to L
2.5
3.6
5.1
ns
tENZLS
Enable-to-Pad Z to L鈥擫ow Slew
11.8
16.9
23.7
ns
tENZH
Enable-to-Pad, Z to H
3.4
4.9
6.9
ns
tENLZ
Enable-to-Pad, L to Z
2.1
3.0
4.2
ns
tENHZ
Enable-to-Pad, H to Z
2.4
5.67
7.94
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.034
0.046
0.066 ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW鈥�
Low Slew
0.05
0.072
0.1
ns/pF
3.3 V LVTTL Output Module Timing1 (VCCI = 3.0 V)
tDLH
Data-to-Pad LOW to HIGH
2.8
4.0
5.6
ns
tDHL
Data-to-Pad HIGH to LOW
2.7
3.9
5.4
ns
tDHLS
Data-to-Pad HIGH to LOW鈥擫ow Slew
9.7
13.9
19.5
ns
tENZL
Enable-to-Pad, Z to L
2.2
3.2
4.4
ns
tENZLS
Enable-to-Pad Z to L鈥擫ow Slew
9.7
13.9
19.6
ns
tENZH
Enable-to-Pad, Z to H
2.8
4.0
5.6
ns
tENLZ
Enable-to-Pad, L to Z
2.8
4.0
5.6
ns
tENHZ
Enable-to-Pad, H to Z
2.6
3.8
5.3
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.02
0.03
0.046 ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW鈥�
Low Slew
0.05
0.072
0.1
ns/pF
5.0 V TTL Output Module Timing* (VCCI = 4.75 V)
tDLH
Data-to-Pad LOW to HIGH
2.0
2.9
4.0
ns
tDHL
Data-to-Pad HIGH to LOW
2.6
3.7
5.2
ns
tDHLS
Data-to-Pad HIGH to LOW鈥擫ow Slew
6.8
9.7
13.6
ns
tENZL
Enable-to-Pad, Z to L
1.9
2.7
3.8
ns
tENZLS
Enable-to-Pad Z to L鈥擫ow Slew
6.8
9.8
13.7
ns
tENZH
Enable-to-Pad, Z to H
2.1
3.0
4.1
ns
tENLZ
Enable-to-Pad, L to Z
3.3
4.8
6.6
ns
Note: *Delays based on 35 pF loading.
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