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參數(shù)資料
| 型號(hào)： | EX256-TQG100I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 30/48頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 12K 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | EX |
| 邏輯元件/單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 81 |
| 門(mén)數(shù)： | 12000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
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TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to
Table 1-4 on page 1-10). Once the boundary scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the “l(fā)ogic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O pins. The “l(fā)ogic reset” state is reached five TCK
cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE
1149.1 specifications.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal
pull-up resistor. This pin functions as an I/O when the Reserve JTAG Reset Pin is not selected in the
Designer software.
VCCI
Supply Voltage
Supply voltage for I/Os.
VCCA
Supply Voltage
Supply voltage for Array.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EX256-TQG100PP | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:eX Family FPGAs |
| EX-257-B-2 | 制造商:COOPER INDUSTRIES 功能描述:EXT 3/8 FMALE SQ DRV 1/4 MALE |
| EX-25-X-B-1-0-16-M16 | 制造商:Amphenol Aerospace 功能描述:CABLE GLAND, AMPHE-EX, SIZE 16 |
| EX-25-X-B-1-0-16-M20 | 制造商:Amphenol Aerospace 功能描述:CABLE GLAND, AMPHE-EX, SIZE 16 |
| EX-25-X-B-1-0-20-M20 | 制造商:Amphenol Aerospace 功能描述:CABLE GLAND, AMPHE-EX, SIZE 20 |
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