Revision 10 1-29 Table 1-19 eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3" />
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鍨嬭櫉锛� EX128-TQG64A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 27/48闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA ANTIFUSE 6K 64-TQFP
妯欐簴鍖呰锛� 160
绯诲垪锛� EX
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 256
杓稿叆/杓稿嚭鏁�(sh霉)锛� 46
闁€鏁�(sh霉)锛� 6000
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eX Family FPGAs
Revision 10
1-29
Table 1-19 eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3 V or 3.0V, TJ = 70掳C)
鈥樷€揚鈥� Speed
鈥楽td鈥� Speed
鈥樷€揊鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
<0.1
ns
tHP
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
357
250
178
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
ns
tRPWH
Min. Pulse Width HIGH
1.4
2.0
2.8
ns
tRPWL
Min. Pulse Width LOW
1.4
2.0
2.8
ns
tRCKSW*
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW*
Maximum Skew (50% Load)
0.2
0.3
ns
tRCKSW*
Maximum Skew (100% Load)
0.1
0.2
ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
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