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eX FPGA Architecture and Characteristics
1-28
Revision 10
Table 1-18 eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3 V, VCCI = 4.75 V, TJ = 70掳C)
鈥揚 Speed
Std Speed
鈥揊 Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
<0.1
ns
tHP
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
357
250
178
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
2.2
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRPWH
Min. Pulse Width HIGH
1.5
2.1
3.0
ns
tRPWL
Min. Pulse Width LOW
1.5
2.1
3.0
ns
tRCKSW*
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW*
Maximum Skew (50% Load)
0.1
0.2
0.3
ns
tRCKSW*
Maximum Skew (100% Load)
0.1
0.2
ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
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