參數(shù)資料
型號(hào)： EVAL-ADV7842EB2Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/28頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADV7842EB2Z
標(biāo)準(zhǔn)包裝： 1
系列： *
ADV7842
Rev. B | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Rating
AVDD to GND
2.2 V
VDD to GND
2.2 V
PVDD to GND
2.2 V
DVDDIO to GND
4.0 V
VDD_SDRAM to GND
4.0 V
CVDD to GND
2.2 V
TVDD to GND
4.0 V
AVDD to PVDD
0.3 V to +0.3 V
AVDD to VDD
0.3 V to +0.3 V
TVDD to CVDD
0.3 V to +2.2 V
DVDDIO to VDD_SDRAM
0.3 V to +3.3 V
VDD_SDRAM to AVDD
0.3 V to +2 V
VDD_SDRAM to VDD
0.3 V to +2 V
Digital Inputs Voltage to GND
0.3 V to DVDDIO + 0.3 V
Digital Outputs Voltage to GND
0.3 V to DVDDIO + 0.3 V
5 V Tolerant Digital Inputs to GND1
5.5 V
Analog Inputs to GND
0.3 V to AVDD + 0.3 V
XTALN and XTALP to GND
0.3 V to PVDD + 0.3 V
Maximum Junction Temperature
(TJ MAX)
125°C
Storage Temperature Range
65°C to +150°C
Infrared Reflow Soldering (20 sec)
260°C
1
The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5,
HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL
and DDCB_SDA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7842, the
user is advised to turn off unused sections of the part.
Due to PCB metal variation, and therefore variation in PCB
heat conductivity, the value of θJA may differ for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the
θ
JA
value.
The maximum junction temperature (TJ MAX) of 125°C must not be
exceeded. The following equation calculates the junction tempera-
ture using the measured package surface temperature and applies
only when no heat sink is used on the device under test (DUT):
(
)
TOTAL
JT
S
J
W
Ψ
T
×
+
=
where:
TS is the package surface temperature (°C).
ΨJT = 0.5°C/W for the 256-ball BGA.
WTOTAL = (PVDD × IPVDD) + (0.4 × TVDD × ITVDD) +
(CVDD × ICVDD) + (AVDD × IAVDD) + (VDD × IVDD) +
(A × DVDDIO × IDVDDIO) + (VDD_SDRAM × IVDD_SDRAM)
where:
0.4 reflects the 40% of TVDD power that is dissipated on the
part itself.
A = 0.5 when the output pixel clock is >74 MHz.
A = 0.75 when the output pixel clock is ≤74 MHz.
ESD CAUTION
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