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| 型號(hào)： | EVAL-ADV7842EB2Z |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 17/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7842EB2Z |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ADV7842
Rev. B | Page 24 of 28
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7842 is highly flexible. The pixel
output bus can support up to 36-bit 4:4:4. The pixel data
supports both single and double data rates modes. In SDR
mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is
possible. In DDR mode, the pixel output port can be configured in
8-/10-/12-bit 4:2:2 modes or 24-/30-/36-bit 4:4:4 modes. Bus
rotation and bus inversion are also supported. All output modes
are controlled via I2C controls.
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include the following:
8-/10-/12-bit ITU-R BT.656 4:2:2 with embedded time
codes and/or HS, VS, and FIELD output signals
SDR 16-/20-/24-/30-/36 bit with embedded time codes
and/or HS/CS and VS/FIELD pin timing
DDR 8-/10-/12-bit 4:2:2 with embedded time codes and/or
HS, VS, and FIELD output signals
DDR 24-/30-/36 bit 4:4:4 with embedded time codes
and/or HS, VS, and FIELD output signals
Note that DDR modes are supported up to 54 MHz by
characterization.
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| EVAL-ADV7844EB1Z | 功能描述:BOARD EVAL FOR ADV7844EB1Z RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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