參數資料
型號: EVAL-ADV7181CLQEBZ
廠商: Analog Devices Inc
文件頁數: 3/20頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADV7181CLQ
標準包裝: 1
主要目的: 視頻,視頻解碼器
已用 IC / 零件: ADV7181CLQ
已供物品:
Data Sheet
ADV7181C
Rev. E | Page 11 of 20
Pin No.
Mnemonic
Type1
Description
33, 45
NC
No Connect. These pins are not connected internally.
34
FB
I
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
35, 36, 46, 47, 48, 49
A
IN1 to AIN6
I
Analog Video Input Channels.
38, 39
CAPY1, CAPY2
I
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
40
AVDD
P
Analog Supply Voltage (3.3 V).
41
REFOUT
O
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor
network for this pin.
42
CML
O
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 9 for a
recommended capacitor network for this pin.
44
CAPC2
I
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
50
SOG/SOY
I
Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
51
RESET
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms
is required to reset the ADV7181C circuitry.
52
ALSB
I
This pin selects the I2C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
53
SDATA
I/O
I2C Port Serial Data Input/Output Pin.
54
SCLK
I
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
55
VS_IN
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
56
HS_IN/CS_IN
I
This pin can be configured in CP mode to be either a digital HS input signal or
a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
63
FIELD/DE
O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin
also can be enabled as a data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
64
VS
O
Vertical Synchronization Output Signal (SDP and CP Modes).
1 G = ground, I = input, O = output, I/O = input/output, and P = power.
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