- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16854 > EVAL-ADV7180LFEBZ (Analog Devices Inc)BOARD EVAL FOR ADV7180 LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADV7180LFEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 67/116頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7180 LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7180 |
| 主要屬性： | CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入 |
| 次要屬性： | 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁(yè)面： | 788 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADV7180BCPZ-REEL-ND - IC VIDEO DECODER SDTV 40-LFCSP ADV7180BSTZ-ND - IC VIDEO DECODER SDTV 64-LQFP ADV7180BCPZ-ND - IC VIDEO DECODER SDTV 40-LFCSP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)當(dāng)前第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
ADV7180
Data Sheet
Rev. I | Page 54 of 116
SYNC PROCESSING
The ADV7180 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits: ENHSPLL and
ENVSPROC.
ENHSPLL, Enable HSYNC Processor, Address 0x01[6]
The HSYNC processor is designed to filter incoming HSYNCs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
Setting ENHSPLL to 0 disables the HSYNC processor.
Setting ENHSPLL to 1 (default) enables the HSYNC processor.
ENVSPROC, Enable VSYNC Processor, Address 0x01[3]
This block provides extra filtering of the detected VSYNCs to
improve vertical lock.
Setting ENVSPROC to 0 disables the VSYNC processor.
Setting ENVSPROC to 1 (default) enables the VSYNC processor.
VBI DATA DECODE
The following are the two VBI data slicers on the ADV7180: the
VBI data processor (VDP) and the VBI System 2.
The VDP can slice both low bandwidth standards and high
bandwidth standards such as teletext. VBI System 2 can slice
low data rate VBI standards only.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, users can read the decoded data bytes
from the I2C registers.
The VBI data standards that can be decoded by the VDP are
listed in Table 67 and Table 68.
Table 67. PAL
Feature
Standard
Teletext System A, C, or D
ITU-R BT.653
Teletext System B/WST
ITU-R BT.653
Video Programming System (VPS)
ETSI EN 300 231 V 1.3.1
Vertical Interval Time Codes (VITC)
Not applicable
Wide Screen Signaling (WSS)
ITU-R BT.1119-1/
ETSI EN.300294
Closed Captioning (CCAP)
Not applicable
Table 68. NTSC
Feature
Standard
Teletext System B and D
ITU-R BT.653
Teletext System C/NABTS
ITU-R BT.653/EIA-516
Vertical Interval Time Codes (VITC)
Not applicable
Copy Generation Management
System (CGMS)
EIA-J CPR-1204/IEC 61880
Gemstar
Not applicable
Closed Captioning (CCAP)
EIA-608
The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default as described in
Table 69. This can be overridden manually and any VBI data can
be decoded on any line. The details of manual programming are
described in Table 70.
VDP Default Configuration
The VDP can decode different VBI data standards on a line-to-
line basis. The various standards supported by default on different
lines of VBI are explained in Table 69.
VDP Manual Configuration
MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64[7], User Sub Map
The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this,
the user must set the MAN_LINE_PGM bit. The user must write
into all the line programming registers, VBI_DATA_Px_Ny and
VBI_DATA_Px (see Register 0x64 to Register 0x77 in Table 108).
When MAN_LINE_PGM to 0 (default) is set, the VDP decodes
default standards on lines, as shown in Table 69.
When MAN_LINE_PGM to 1 is set, the VBI standards to be
decoded are manually programmed.
VBI_DATA_Px_Ny[3:0], VBI_DATA_Px[3:0], VBI
Standard to be Decoded on Line X for PAL, Line Y for
NTSC, Address 0x64 to Address 0x77, User Sub Map
These are related 4-bit clusters in Register 0x64 to Register 0x77
of the user sub map. These 4-bit, line programming registers,
VBI_DATA_Px_Ny and VBI_DATA_Px, identify the VBI data
standard that are decoded on Line X in PAL mode or on Line Y
in NTSC mode. The different types of VBI standards decoded
by VBI_DATA_Px_Ny and VBI_DATA_Px are shown in Table 70.
Note that the X or Y value depends on whether the ADV7180 is
in PAL or NTSC mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V110C36C100BL | CONVERTER MOD DC/DC 36V 100W |
| RNF-100-MINI-SPL-1/8-BK | HEATSHRINK RNF-100 1/8"X60' BLK |
| MLF2012DR18M | INDUCTOR MULTILAYER .18UH 0805 |
| RNF-100-2-BK-STK | HEATSHRINK RNF-100 2"X4' BLK |
| ECM31DCMH-S288 | CONN EDGECARD 62POS .156 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV7180LQEBZ | 功能描述:BOARD EVALUATION ADV7180 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081 |
| EVAL-ADV7181CLFEBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Boxed Product (Development Kits) |
| EVAL-ADV7181CLQEBZ | 功能描述:BOARD EVAL FOR ADV7181CLQ RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADV7181DEBZ | 功能描述:EVAL BOARD FOR ADV7181D RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADV7181EBM | 制造商:Analog Devices 功能描述:UNRELEASED EVAL BOARD I.C. - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。