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| 型號(hào)： | EVAL-ADUC824QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/68頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC824 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC824 |
| 所含物品： | 評(píng)估板，線纜，電源，軟件和文檔 |
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REV. B
ADuC824
–20–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
No.
Mnemonic
Type
*
Description
22–25
P3.4–P3.7
I/O
P3.4–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s
written to them are pulled high by the internal pull-up resistors, and in that state can be used as
inputs. As inputs, Port 3 pins being pulled externally low will source current because of the
internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for
two core clock periods of the instruction cycle. The secondary functions of Port 3 pins are:
P3.4/T0
I/O
Timer/Counter 0 Input
P3.5/T1
I/O
Timer/Counter 1 Input
P3.6/
WR
I/O
Write Control Signal, Logic Output. Latches the data byte from Port 0 into an external data memory.
P3.7/
RD
I/O
Read Control Signal, Logic Output. Enables the data from an external data memory to Port 0.
26
SCLK
I/O
Serial interface clock for either the I
2C-compatible or SPI interface. As an input this pin is a Schmitt-
triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low.
27
SDATA/MOSI
I/O
Serial data I/O for the I
2C compatible interface or master output/slave input for the SPI interface.
A weak internal pull-up is present on this pin unless it is outputting logic low.
28 – 31
P2.0 – P2.3
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s (A8–A11)
written to them are pulled high by the internal pull-up resistors, and in that state can (A16–A19)
be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because
of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from
external program memory and middle and high order address bytes during accesses to the 24-bit
external data memory space.
32
XTAL1
I
Input to the crystal oscillator inverter
33
XTAL2
O
Output from the crystal oscillator inverter
36 – 39
P2.4 – P2.7
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s (A12–A15)
written to them are pulled high by the internal pull-up resistors, and in that state they (A20–A23)
can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches
from external program memory and middle and high order address bytes during accesses to the
24-bit external data memory space.
40
EA
I/O
External Access Enable, Logic Input. When held high, this input enables the device to fetch
code from internal program memory locations 0000H to 1FFFH. When held low, this input
enables the device to fetch all instructions from external program memory. To determine the
mode of code execution, i.e., internal or external, the
EA pin is sampled at the end of an external
RESET assertion or as part of a device power cycle.
EA may also be used as an external emula-
tion I/O pin and therefore the voltage level at this pin must not be changed during normal mode
operation as it may cause an emulation interrupt that will halt code execution.
41
PSEN
O
Program Store Enable, Logic Output. This output is a control signal that enables the external
program memory to the bus during external fetch operations. It is active every six oscillator
periods except during external data memory accesses. This pin remains high during internal
program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a device power cycle.
42
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for
24-bit data address space accesses) of the address to external memory during external code or
data memory access cycles. It is activated every six oscillator periods except during an external
data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR.
43 – 46
P0.0 – P0.3
I/O
P0.0 – P0.3 pins are part of Port 0, which is an 8-bit open-drain bidirectional.
(AD0 – AD3)
I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance
inputs. An external pull-up resistor will be required on P0 outputsto force a valid logic high level
externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external
program or data memory. In this application it uses strong internal pull-ups when emitting 1s.
49 – 52
P0.4 – P0.7
I/O
P0.4 – P0.7 pins are part of Port 0, which is an 8-bit open drain bidirectional.
(AD4 – AD7)
I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance
inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external
program or data memory. In this application it uses strong internal pull-ups when emitting 1s.
*I = Input, O = Output, S = Supply
NOTES
1. In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated.
2. In the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC824 hardware unless otherwise stated.
3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products.
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