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| 型號： | EVAL-ADUC7126QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 設(shè)計資源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7126 |
| 所含物品： | 板 |
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Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 53 of 108
DACBKEY1 Register
Name:
DACBKEY1
Address:
0xFFFF0650
Default Value:
0x0000
Access:
Write
DACBKEY2 Register
Name:
DACBKEY2
Address:
0xFFFF0658
Default Value:
0x0000
Access:
Write
POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the
ADuC7124/ADuC7126. It indicates when the IOVDD supply pin
drops below one of two supply trip points. The monitor
function is controlled via the PSMCON register. If enabled in
the IRQEN or FIQEN register, the monitor interrupts the core
using the PSMI bit in the PSMCON MMR. This bit is immediately
cleared when CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level is established.
PSMCON Register
Name:
PSMCON
Address:
0xFFFF0440
Default Value:
0x0008
Access:
Read/write
Table 68. PSMCON MMR Bit Descriptions
Bit
Name
Description
3
CMP
Comparator bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above
its selected trip point or that the PSM is in
power-down mode. Read 0 indicates that the
IOVDD supply is below its selected trip point. This
bit should be set before leaving the interrupt
service routine.
2
TP
Trip point selection bits.
0 = 2.79 V, 1 = 3.07 V.
1
PSMEN
Power supply monitor enable bit.
Set to 1 to enable the power supply monitor
circuit.
Clear to 0 to disable the power supply monitor
circuit.
0
PSMI
Power supply monitor interrupt bit. This bit is set
high by the MicroConverter when CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. When CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared when CMP goes high.
COMPARATOR
The ADuC7124/ADuC7126 integrate a voltage comparator. The
positive input is multiplexed with ADC2, and the negative input
has two options: ADC3 or DAC0. The output of the comparator
can be configured to generate a system interrupt, be routed
directly to the programmable logic array, start an ADC conver-
09
12
3-
2
25
MUX
IRQ
MUX
DAC0
ADC2/CMP0
ADC3/CMP1
P0.0/CMPOUT
Figure 43. Comparator
Hysteresis
Figure 44 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is the width of the hysteresis range.
091
23
-06
3
CMPOUT
COMP0
VH
VOS
Figure 44. Comparator Hysteresis Transfer Function
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