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| 型號： | EVAL-ADUC7126QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7126 |
| 設(shè)計資源： | EVAL-ADUC7126 Schematic ADUC7126 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7126 |
| 所含物品： | 板 |
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Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 49 of 108
Table 59. REMAP MMR Bit Descriptions
(Address = 0xFFFF0220. Default Value = 0x00)
Bit
Name
Description
0
Remap
Remap bit.
Set by the user to remap the SRAM to Address
0x00000000.
Cleared automatically after reset to remap the
Flash/EE memory to Address 0x00000000.
Remap Operation
When a reset occurs on the ADuC7124/ADuC7126, execution
automatically starts in factory programmed, internal
configuration code. This kernel is hidden and cannot be accessed
by user code. If the part is in normal mode (BM pin is high), it
executes the power-on configuration routine of the kernel and
then jumps to the reset vector address, 0x00000000, to execute
the reset exception routine of the user.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset interrupt routine must always be written
in Flash/EE.
The remap is done from Flash/EE by setting Bit 0 of the REMAP
register. Caution must be taken to execute this command from
Flash/EE, above Address 0x00080020, and not from the bottom
of the array, because this is replaced by the SRAM.
This operation is reversible. The Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the REMAP MMR.
Caution must again be taken to execute the remap function
from outside the mirrored area. Any type of reset remaps the
Flash/EE memory at the bottom of the array.
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiation, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default Value:
0x01
Access:
Read only
Table 60. RSTSTA MMR Bit Descriptions
Bit
Description
[7:3]
Reserved.
2
Software reset.
Set by the user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
1
Watchdog timeout.
Set automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Default Value:
0x00
Access:
Write only
Note that to clear the RSTSTA register, users must write the
Value 0x07 to the RSTCLR register.
RSTCFG Register
Name:
RSTCFG
Address:
0xFFFF024C
Default Value:
0x05
Access:
Read/write
Table 61. RSTCFG MMR Bit Descriptions
Bit
Description
[7:3]
Reserved. Always set to 0.
2
This bit is set to 1 to configure the DAC outputs to
retain their state after a watchdog or software reset.
This bit is cleared for the DAC pins and registers to
return to their default state.
1
Reserved. Always set to 0.
0
This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
The RSTCFG write sequence is as follows:
1.
Write Code 0x76 to Register RSTKEY1.
2.
Write user value to Register RSTCFG.
3.
Write Code 0xB1 to Register RSTKEY2.
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