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| 型號： | EVAL-ADUC7121QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/96頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADUC7121 |
| 設(shè)計資源： | ADUC7121 Gerber Files ADUC7121 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADUC7121 |
| 所含物品： | 板，CD |
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ADuC7121
Data Sheet
Rev. B | Page 34 of 96
POWER SUPPLY MONITOR
The power supply monitor on the ADuC7121 indicates when
the IOVDD supply pin drops below one of two supply trip
points. The monitor function is controlled via the PSMCON
register. If enabled in the IRQEN or FIQEN register, the monitor
interrupts the core using the PSMI bit in the PSMCON MMR.
This bit is cleared immediately after CMP goes high. Note that
if the interrupt generated is exited before CMP goes high
(IOVDD supply voltage is above the trip point), no further
interrupts are generated until CMP returns high. The user
needs to ensure that the code execution remains within the ISR
until CMP returns high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brownout con-
ditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
The PSM does not operate correctly when using JTAG debug;
therefore, disable PSM while in JTAG debug mode.
Table 40. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x0008)
Bit
Name
Description
15:4
Reserved
These bits are reserved.
3
CMP
Comparator bit. This is a read-only bit that directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above its selected trip point or the PSM is in power-down mode.
Read 0 indicates the IOVDD supply is below its selected trip point. Set this bit before leaving the interrupt
service routine.
2
TP
Trip point selection bit.
0 = 2.79 V.
1 = 3.07 V.
1
PSMEN
Power supply monitor enable bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
0
PSMI
Power supply monitor interrupt bit. This bit is set high by the MicroConverter if CMP is low, indicating low
I/O supply. The PSMI bit can be used to interrupt the processor. When CMP returns high, the PSMI bit can
be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be
cleared immediately after CMP goes high.
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