參數(shù)資料
型號(hào)： EVAL-ADUC7029QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/104頁(yè)
文件大?。?/td> 0K
描述： EVAL DEV SYSTEM FOR ADUC7029
設(shè)計(jì)資源： ADuC70xx Serial Download Protocol
ADuC7029 Dev System Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 26 of 104
Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP)
Pin No.
Mnemonic
Description
1
ADC4
Single-Ended or Differential Analog Input 4.
2
ADC5
Single-Ended or Differential Analog Input 5.
3
ADC6
Single-Ended or Differential Analog Input 6.
4
ADC7
Single-Ended or Differential Analog Input 7.
5
ADC8
Single-Ended or Differential Analog Input 8.
6
ADC9
Single-Ended or Differential Analog Input 9.
7
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
8
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
9
DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present
on the ADuC7025.
10
DAC1/ADC13
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present
on the ADuC7025.
11
TMS
JTAG Test Port Input, Test Mode Select. Debug and download access.
12
TDI
JTAG Test Port Input, Test Data In. Debug and download access
13
P4.6/PLAO[14]
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
14
P4.7/PLAO[15]
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
15
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and execute code if BM is pulled high at reset through a 1 k resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
16
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-
On Reset Output/Programmable Logic Array Output Element 3.
17
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
18
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
19
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
20
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
21
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 F
capacitor to DGND only.
22
DGND
Ground for Core Logic.
23
P3.0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic
Array Input Element 8.
24
P3.1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic
Array Input Element 9.
25
P3.2/PWM1H/PLAI[10]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic
Array Input Element 10.
26
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic
Array Input Element 11.
27
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output.
28
RST
Reset Input, Active Low.
29
P3.4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic
Array Input 12.
30
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic
Array Input Element 13.
31
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
32
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
33
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
34
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
35
XCLKO
Output from the Crystal Oscillator Inverter.
36
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
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