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參數(shù)資料
| 型號： | EVAL-ADF411XEBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF411X NO CHIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4001，ADF4106，ADF4107，ADF4110，ADF4111，ADF4112，ADF4113，ADF4116，ADF4117，ADF4118，ADF4153 |
| 主要屬性： | 單路分?jǐn)?shù)-N 或整數(shù)-N PLL |
| 次要屬性： | 板不包括環(huán)路濾波器、合成器和 VCO |
| 已供物品： | 部分安裝的板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4112BCPZ-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BCPZ-RL-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4111BRUZ-RL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4111BRUZ-RL-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4112BCPZ-RL7-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4111BRUZ-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4113BCPZ-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4110BRUZ-RL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP 更多... |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 25 of 28
DIRECT CONVERSION MODULATOR
In some applications, a direct conversion architecture can be
used in base station transmitters. Figure 37 shows the combina-
tion available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The local oscillator (LO) is implemented using the ADF4113. In
this case, the OSC 3B1-13M0 provides the stable 13 MHz
reference frequency. The system is designed for a 200 kHz
channel spacing and an output center frequency of 1960 MHz.
The target application is a WCDMA base station transmitter.
Typical phase noise performance from this LO is 85 dBc/Hz at
a 1 kHz offset.
The LO port of the AD8346 is driven in single-ended fashion.
LOIN is ac-coupled to ground with the 100 pF capacitor; LOIP
is driven through the ac coupling capacitor from a 50 source.
An LO drive level of between 6 dBm and 12 dBm is required.
The circuit of Figure 37 gives a typical level of 8 dBm.
The RF output is designed to drive a 50 load but must be ac-
coupled as shown in Figure 37. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power is
around 10 dBm.
RSET
ADF4113
18
100pF
18
REFIN
100pF
RFINA
RFINB
CP
SERIAL
DIGITAL
INTERFACE
TCXO
OSC 3B1-13M0
100pF
620pF
3.9k
3.3k
9.1nF
4.7k
18
100pF
RFOUT
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM TO INCREASE CLARITY.
AD9761
TxDAC
REFIO
FS ADJ
MODULATED
DIGITAL
DATA
QOUTB
IOUTA
IOUTB
QOUTA
AD8346
LOIN
LOIP
VOUT
100pF
2k
51
910pF
VCO190-1960T
IBBP
IBBN
QBBP
QBBN
LOW-PASS
FILTER
LOW-PASS
FILTER
03496-0-042
Figure 37. Direct Conversion Transmitter Solution
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