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| 型號： | EVAL-ADF4113HVEB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4113HV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4113HV |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 4GHz 高壓充電泵 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADF4113BCPZ-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113HVBRUZ-RL7-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBRUZ-RL-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-RL7-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBCPZ-RL-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBRUZ-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113BRUZ-REEL7TR-ND - IC SYNTHESZR FREQ PLL RF 16TSSOP 更多... |
Data Sheet
ADF4113HV
Rev. B | Page 3 of 20
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k; dBm referred to 50 ;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: 40°C to +85°C.
Table 1.
Parameter
BVersion
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
15/0
dBm min/max
RF Input Frequency
0.2/3.7
GHz min/max
For lower frequencies, ensure SR > 130 V/μs
Prescaler Output Frequency2
165
MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
10/0
dBm min/max
RF Input Frequency
0.2/3.7
GHz min/max
For lower frequencies, ensure SR > 130 V/s
0.2/4.0
GHz min/max
Input level = 5 dBm
Prescaler Output Frequency
200
MHz max
REF
IN CHARACTERISTICS
REF
IN Input Frequency
5/150
MHz min/max
For f < 5 MHz, ensure SR > 100 V/s
Reference Input Sensitivity
0.4/AV
DD
0.4/AV
DD
V p-p min/max
AV
1.0/AV
DD
1.0/AV
DD
V p-p min/max
For f ≥ 10 MHz, AV
DD = 5 V, biased at AVDD/2
REF
IN Input Capacitance
10
pF max
REF
IN Input Current
±100
A max
PHASE DETECTOR FREQUENCY
5
MHz max
CHARGE PUMP
I
CP Sink/Source
R
SET = 4.7 k
High Value
640
μA typ
Low Value
80
A typ
Absolute Accuracy
2.5
% typ
R
SET Range
3.9/10
k typ
I
CP Three-State Leakage Current
5
nA max
Sink and Source Current Matching
3
% typ
1 V ≤ V
CP ≤ VP – 1 V
I
CP vs. VCP
1.5
% typ
1 V ≤ V
CP ≤ VP – 1 V
I
CP vs. Temperature
2
% typ
V
CP = VP/2
LOGIC INPUTS
V
INH, Input High Voltage
0.8 × DV
DD
0.8 × DV
DD
V min
V
INL, Input Low Voltage
0.2 × DV
DD
0.2 × DV
DD
V max
I
INH/IINL, Input Current
±1
A max
C
IN, Input Capacitance
10
pF max
LOGIC OUTPUTS
V
OH, Output High Voltage
DV
DD 0.4
DV
DD 0.4
V min
I
OH = 500 A
V
OL, Output Low Voltage
0.4
V max
I
OL = 500 A
POWER SUPPLIES
AV
DD
2.7/5.5
V min/V max
DV
DD
AV
DD
AV
DD
V
P
13.5/16.5
V min/V max
I
5 (AI
DD + DIDD)
16
11
mA max
11 mA typical
I
P
0.25
mA max
T
A = 25°C
Low Power Sleep Mode
1
A typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor6
212
dBc/Hz typ
1 The B chip specifications are given as typical values.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AC coupling ensures AV
DD/2 bias.
4 Guaranteed by characterization.
5 T
A = 25
oC; AV
DD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT, and subtracting 20logN (where N is the N divider
value) and 10logfPFD: PNSYNTH = PNTOT 10logfPFD 20logN.
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