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參數(shù)資料
| 型號(hào)： | EVAL-ADF4112EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4112 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4112 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 836MHz CDMA 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4112BCPZ-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BCPZ-RL-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BCPZ-RL7-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BRUZ-REEL7-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4112BRUZ-REEL-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4112BRUZ-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP ADF4112BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4112BRU-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 21 of 28
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits,
DB22 and DB21, which are labeled DLY and SYNC,
respectively. These bits affect the operation of the prescaler.
With SYNC = 1, the prescaler output is resynchronized with the
RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB
improvement is seen in the ADF4113. The lower bandwidth
devices can show an even greater improvement. For example,
the ADF4110 phase noise is typically improved by 3 dB when
SYNC is enabled.
With DLY = 1, the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
down. It is important to be aware of this when using the SYNC
feature. Adding a delay to the RF signal, by programming
DLY = 1, extends the operating frequency and temperature
somewhat. Using the SYNC feature also increases the value of
the AIDD for the device. With a 900 MHz output, the ADF4113
AIDD increases by about 1.3 mA when SYNC is enabled and by
an additional 0.3 mA if DLY is enabled.
All the typical performance plots in this data sheet, except for
Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-
tion or delay enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4113EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM900 Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF4113EB2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1750MHz Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF4113EBZ1 | 功能描述:BOARD EVAL FOR ADF4113 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4113EBZ2 | 功能描述:BOARD EVAL FOR ADF4113 1750MHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADF4113HVEB1Z | 功能描述:BOARD EVALUATION FOR ADF4113HV RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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