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參數(shù)資料
| 型號： | EVAL-ADF4112EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4112 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4112 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 836MHz CDMA 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關產(chǎn)品： | ADF4112BCPZ-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BCPZ-RL-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BCPZ-RL7-ND - IC PLL FREQ SYNTH 3GHZ 20-LFCSP ADF4112BRUZ-REEL7-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4112BRUZ-REEL-ND - IC PLL RF FREQ SYNTHESZR 16TSSOP ADF4112BRUZ-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP ADF4112BRU-REEL7-ND - IC PLL FREQ SYNTHESIZER 16-TSSOP ADF4112BRU-ND - IC SYNTH PLL RF 3.0GHZ 16-TSSOP |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 19 of 28
FUNCTION LATCH
The on-chip function latch is programmed with C2, C1 set to 1.
Table 9 shows the input data format for programming the
function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in “close” alignment with
the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF411x provide
program-mable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1,
provided PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once power-down is enabled by writing a 1
into Bit PD1 (provided a 1 has also been loaded to PD2), the
device goes into power-down on the next charge pump event.
When a power-down is activated (either synchronous or
asynchronous mode including CE pin activated power-down),
the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4110 family. Table 9 shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Fastlock is
enables only when this is 1.
Fastlock Mode Bit
DB10 of the function latch is the fastlock enable bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if
the fastlock mode bit is 1, fastlock mode 2 is selected.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock by having a
0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock by having a 1 written to the
CP gain bit in the AB counter latch. The device exits fastlock
under the control of the timer counter. After the timeout period
determined by the value in TC4 through TC1, the CP gain bit in
the AB counter latch is automatically reset to 0 and the device
reverts to normal mode instead of fastlock. See Table 9 for the
timeout periods.
Timer Counter Control
The user has the option of programming two charge pump cur-
rents. Current Setting 1 is meant to be used when the RF output
is stable and the system is in a static state. Current Setting 2 is
meant to be used when the system is dynamic and in a state of
change (i.e., when a new output frequency is programmed).
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump
currents are going to be. For example, they may choose 2.5 mA
as Current Setting 1 and 5 mA as Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 through DB11 (TC4 through TC1) in the function latch.
The truth table is given in Table 10.
A user can program a new output frequency simply by pro-
gramming the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6–CPI4 for a period deter-
mined by TC4 through TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time, the CP gain bit in the AB counter latch is reset to 0
and is ready for the next time the user wishes to change the
frequency.
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