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參數(shù)資料
| 型號(hào)： | EVAL-AD9880-ABZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要屬性： | HDMI 接收器和模擬接口 |
| 次要屬性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 47 of 64
0x28
1-0
Hsync Delay MSBs
Along with the eight bits following these ten bits set
the delay (in pixels) from the Hsync leading edge to
the start of active video. The power-up default setting
is 0x104.
0x29
7-0
Hsync Delay LSBs
See the Hsync Delay MSBs section.
0x2A
3-0
Line Width MSBs
Along with the 8 bits following these 12 bits, set the
width of the active video line (in pixels). The power-
up default setting is 0x500.
0x2B
7-0
Line Width LSBs
See the line width MSBs section.
0x2C
3-0
Screen Height MSBs
Along with the 8 bits following these 12 bits, set the
height of the active screen (in lines). The power-up
default setting is 0x2D0.
0x2D
7-0
Screen Height LSBs
See the Screen Height MSBs section.
0x2E
7
Ctrl Enable
When set, this bit allows Ctrl [3:0] signals decoded
from the DVI to be output on the I2S data pins. The
power-up default setting is 0.
Table 64. CTRL Enable.
Select
Result
0
I2S signals on I2S lines
1
Ctrl [3:0] output on I2S lines
0x2E
6-5
I2S Output Mode
These bits select between four options for the I2S
output: I2S, right-justified, left-justified, or raw
IEC60958 mode. The power-up default setting is 00.
Table 65. I2S Output Select
I2S Output Mode
Result
00
I2S mode
01
Right-Justified
10
Left-Justified
11
Raw IEC60958 mode
0x2E
4-0
I2S Bit Width
These bits set the I2S bit width for right-justified
mode. The power-up default setting is 24 bits.
0x2F
6
TMDS Sync Detect
This read-only bit indicates the presence of a TMDS
DE.
Table 66. Detected TMDS Sync Results
Detect
Result
0
No TMDS DE present
1
TMDS DE detected
0x2F
5
TMDS Active
This read only bit indicates the presence of a TMDS
clock.
Table 67. Detected TMDS Clock Results
Detect
Result
0
No TMDS clock present
1
TMDS clock detected
0x2F
4
AV Mute
This read-only bit indicates the presence of AV (audio
video) mute based on general control packets.
Table 68. Detected AV Mute Status
Detect
Result
0
AV not muted
AV muted
0x2F
3
HDCP Keys Read
This read-only bit reports if the HDCP keys were read
successfully.
Table 69. HDCP Keys
Detect
Result
0
Failure to read HDCP keys
1
HDCP keys read
0x2F
2-0
HDMI Quality
These read-only bits indicate a level of HDMI quality
based on the DE (display enable) edges. A larger
number indicates a higher quality.
0x30
6
HDMI Content Encrypted
This read-only bit is high when HDCP decryption is
in use (content is protected). The signal goes low
when HDCP is not being used. Customers can use this
bit to determine whether or not to allow copying of
the content. The bit should be sampled at regular
intervals since it can change on a frame by frame
basis.
Table 70. HDCP Activity
Detect
Result
0
HDCP not in use
1
HDCP decryption in use
0x30
5
DVI Hsync Polarity
This read-only bit indicates the polarity of the DVI
Hsync.
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