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參數(shù)資料
| 型號： | EVAL-AD9835SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9835 |
| 標準包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9835 |
| 已供物品： | 板 |
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Data Sheet
AD9835
Rev. A | Page 17 of 28
Table 12. Setting SYNC and SELSRC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
SYNC
SELSRC
X1
X1
X1
X1
1 X = don’t care.
Table 13. Power-Down, Resetting and Clearing the AD9835
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
SLEEP
RESET
CLR
X1
X1
1 X = don’t care.
Transfer of the data from the 16-bit data register to the
destination register or from the FSELECT/PSEL register to the
respective multiplexer occurs on the next MCLK rising edge.
Because SCLK and MCLK are asynchronous, an MCLK rising
edge may occur while the data bits are in a transitional state.
This can cause a brief spurious DAC output if the register being
written to is generating the DAC output. To avoid such spurious
outputs, the AD9835 contains synchronizing circuitry.
When the SYNC bit is set to 1, the synchronizer is enabled and
data transfers from the serial register (defer register) to the 16-bit
data register, and the FSELECT/PSEL registers occur following
a two-stage pipeline delay that is triggered on the MCLK falling
edge. The pipeline delay ensures that the data is valid when the
transfer occurs. Similarly, selection of the frequency/phase
registers using the FSELECT/PSELx pins is synchronized with
the MCLK rising edge when SYNC = 1. When SYNC = 0, the
synchronizer is bypassed.
Selecting the frequency/phase registers using the pins is
synchronized with MCLK internally also when SYNC = 1 to
ensure that these inputs are valid at the MCLK rising edge. If
times t11 and t11A are met, then the inputs will be at steady state
at the MCLK rising edge. However, if times t11 and t11A are
violated, the internal synchronizing circuitry will delay the
instant at which the pins are sampled, ensuring that the inputs
are valid at the sampling instant (see Figure 5).
LATENCY
Associated with each operation is a latency. When inputs
FSELECT/PSEL change value, there is a pipeline delay before
control is transferred to the selected register; there is a pipeline
delay before the analog output is controlled by the selected
register. When times t11 and t11A are met, PSEL0, PSEL1, and
FSELECT have latencies of six MCLK cycles when SYNC = 0.
When SYNC = 1, the latency is increased to 8 MCLK cycles.
When times t11 and t11A are not met, the latency can increase by
one MCLK cycle. Similarly, there is a latency associated with
each write operation. If a selected frequency/phase register is
loaded with a new word, there is a delay of 6 to 7 MCLK cycles
before the analog output will change (there is an uncertainty of
one MCLK cycle regarding the MCLK rising edge at which the
data is loaded into the destination register). When SYNC = 1,
the latency is 8 or 9 MCLK cycles.
FLOWCHARTS
The flowchart in Figure 22 shows the operating routine for the
reset, which resets the phase accumulator to zero so that the
analog output is at midscale. To avoid spurious DAC outputs
while the AD9835 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high sets SYNC and SELSRC to 0 so that the
FSELECT/PSELx pins are used to select the frequency/phase
registers, and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable the
synchronization circuitry or to change control to the FSELECT/
PSEL bits.
RESET does not reset the phase and frequency registers. These
registers will contain invalid data and, therefore, should be set to
a known value by the user. The RESET bit is then set to 0 to begin
generating an output. A signal will appear at the DAC output 6
MCLK cycles after RESET is set to 0.
The analog output is fMCLK/232 × FREG, where FREG is the value
loaded into the selected frequency register. This signal is phase
shifted by the amount specified in the selected phase register
(2π/4096 × PHASEx REG, where PHASEx REG is the value
contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
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