參數(shù)資料
型號： EVAL-AD9835SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/28頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9835
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9835
已供物品： 板
AD9835
Data Sheet
Rev. A | Page 16 of 28
Table 8. Control Registers
Register
Size
Description
FREQ0 REG
32 bits
Frequency Register 0. This defines the
output frequency, when FSELECT = 0,
as a fraction of the MCLK frequency.
FREQ1 REG
32 bits
Frequency Register 1. This defines the
output frequency, when FSELECT = 1,
as a fraction of the MCLK frequency.
PHASE0 REG
12 bits
Phase Offset Register 0. When PSEL0 =
PSEL1 = 0, the contents of this register
are added to the output of the phase
accumulator.
PHASE1 REG
12 bits
Phase Offset Register 1. When PSEL0 = 1
and PSEL1 = 0, the contents of this
register are added to the output of the
phase accumulator.
PHASE2 REG
12 bits
Phase Offset Register 2. When PSEL0 = 0
and PSEL1 = 1, the contents of this
register are added to the output of the
phase accumulator.
PHASE3 REG
12 bits
Phase Offset Register 3. When PSEL0 =
PSEL1 = 1, the contents of this register
are added to the output of the phase
accumulator.
Table 9. 32-Bit Frequency Word
16 MSBs
16 LSBs
8 H MSBs
8 L MSBs
8 H LSBs
8 L LSBs
Table 10. 12-Bit Frequency Word
8 LSBs
4 MSBs (The 4 MSBs of the
8-Bit Word Loaded = 0)
DIRECT DATA TRANSFER AND DEFERRED DATA
TRANSFER
Within the AD9835, 16-bit transfers are used when loading the
destination frequency/phase register. There are two modes for
loading a register, direct data transfer and a deferred data transfer.
With a deferred data transfer, the 8-bit word is loaded into the
defer register (8 LSBs or 8 MSBs). However, this data is not
loaded into the 16-bit data register; therefore, the destination
register is not updated. With a direct data transfer, the 8-bit word
is loaded into the appropriate defer register (8 LSBs or 8 MSBs).
Immediately following the loading of the defer register, the
contents of the complete defer register are loaded into the 16-bit
data register and the destination register is loaded on the next
MCLK rising edge. When a destination register is addressed, a
deferred transfer is needed first followed by a direct transfer.
When all 16 bits of the defer register contain relevant data, the
destination register can then be updated using 8-bit loading
rather than 16-bit loading, that is, direct data transfers can
be used.
For example, after a new 16-bit word has been loaded to
a destination register, the defer register will also contain this
word. If the next write instruction is to the same destination
register, the user can use direct data transfers immediately.
When writing to a phase register, the 4 MSBs of the 16-bit word
loaded into the data register should be zero (the phase registers
are 12 bits wide).
To alter the entire contents of a frequency register, four write
operations are needed. However, the 16 MSBs of a frequency
word are contained in a separate register to the 16 LSBs.
Therefore, the 16 MSBs of the frequency word can be altered
independent of the 16 LSBs.
The phase and frequency registers to be used are selected using
the FSELECT, PSEL0, and PSEL1 pins, or the corresponding
bits can be used. Bit SELSRC determines whether the bits or the
pins are used. When SELSRC = 0, the pins are used, and when
SELSRC = 1, the bits are used. When CLR is taken high,
SELSRC is set to 0 so that the pins are the default source. Data
transfers from the serial (defer) register to the 16-bit data register,
and the FSELECT and PSEL registers, occur following the 16th
falling SCLK edge.
Table 11. Controlling the AD9835
D15
D14
Command
1
0
Selects source of control for the PHASEx and
FREQx registers and enables synchronization.
Bit D13 is the SYNC bit. When this bit is high,
reading of the FSELECT, PSEL0, and PSEL1 bits/
pins and the loading of the destination register
with data is synchronized with the rising edge of
MCLK. The latency is increased by 2 MCLK cycles
when SYNC = 1. When SYNC = 0, the loading of the
data and the sampling of FSELECT/PSEL0/PSEL1
occurs asynchronously.
Bit D12 is the select source bit (SELSRC). When this
bit equals 1, the PHASEx/FREQx REG is selected
using the FSELECT, PSEL0, and PSEL1 bits. When
SELSRC = 0, the PHASEx/FREQx REG is selected
using the FSELECT, PSEL0, and PSEL1 pins.
1
SLEEP, RESET, and CLR (clear).
D13 is the SLEEP bit. When this bit equals 1, the
AD9835 is powered down, internal clocks are
disabled, and the current sources and REFOUT of
the DAC are turned off. When SLEEP = 0, the
AD9835 is powered up. When RESET (D12) = 1, the
phase accumulator is set to zero phase that
corresponds to an analog output of midscale.
When CLR (D11) = 1, SYNC and SELSRC are set to
zero. CLR resets to 0 automatically.
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