參數(shù)資料
型號(hào)： EVAL-AD7688SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7688
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 3.75mW @ 100kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7688
已供物品： 板
AD7688
Rev. A | Page 22 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7688s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7688s is shown
in Figure 44 and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
Figure 44) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7688 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7688s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7688s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
02973-
043
CNV
SCK
SDO
SDI
AD7688
C
CNV
SCK
SDO
SDI
AD7688
A
CNV
SCK
SDO
SDI
AD7688
B
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
SDOA = SDIB
DA15 DA14 DA13
SCK
123
35
47
48
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
415
tSCK
tSCKH
tSCKL
DA0
17
34
16
SDOB = SDIC
DB15 DB14 DB13
DA1
DB1DB0DA15 DA14
49
tSSDISCK
tHSDISC
tHSDO
tDSDO
SDOC
DC15 DC14 DC13
DA1DA0
DC1DC0DA14
19
31
32
18
33
DB1DB0DA15
DB15 DB14
tDSDOSDI
tSSCKCNV
tHSCKCNV
02973-044
DA0
tDSDOSDI
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
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