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| 型號： | EVAL-AD7688SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7688 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 3.75mW @ 100kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7688 |
| 已供物品： | 板 |
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AD7688
Rev. A | Page 20 of 28
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7688 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 40 and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7688 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
02973-
039
47k
Ω
CNV
SCK
SDO
SDI
AD7688
Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram
SDO
D15
D14
D1
D0
tDIS
SCK
12
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
02973-
040
Figure 41. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
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