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參數(shù)資料
型號(hào)： EVAL-AD7663CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7663
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±4 REF
在以下條件下的電源（標(biāo)準(zhǔn)）： 35mW @ 250kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7663
已供物品： 板，CD
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AD7663ASTZRL-ND - IC ADC 16BIT CMOS 48-LQFP T/R
AD7663ASTZ-ND - IC ADC 16BIT CMOS 48-LQFP
REV. B
–3–
AD7663
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
t1
5ns
Time between Conversions
t2
4s
CNVST LOW to BUSY HIGH Delay
t3
30
ns
BUSY HIGH All Modes Except in
t4
1.25
s
Master Serial Read after Convert Mode
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
1.25
s
Acquisition Time
t8
2.75
s
RESET Pulsewidth
t9
10
ns
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
1.25
s
DATA Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Read during Convert)
t17
0.5
s
SYNC Asserted to SCLK First Edge Delay
2
t18
4ns
Internal SCLK Period
2
t19
25
40
ns
Internal SCLK HIGH
2
t20
15
ns
Internal SCLK LOW
2
t21
9.5
ns
SDOUT Valid Setup Time
2
t22
4.5
ns
SDOUT Valid Hold Time
2
t23
2ns
SCLK Last Edge to SYNC Delay
2
t24
3ns
Parameter
Conditions
Min
Typ
Max
Unit
TEMPERATURE RANGE
8
Specified Performance
TMIN to TMAX
–40
+85
°C
NOTES
1LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 V.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5Tested in Parallel Reading Mode.
6Tested with the 0 V to 5 V range and V
IN – VINGND = 0 V. See Power Dissipation section.
7With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
8Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Input
Range
IND(4R)
INC(4R)
INB(2R)
INA(R)
Impedance
1
±4 REF
2
VIN
INGND
REF
5.85 k
W
±2 REF
VIN
INGND
REF
3.41 k
W
±REF
VIN
REF
2.56 k
W
0 V to 4 REF
VIN
INGND
3.41 k
W
0 V to 2 REF
VIN
INGND
2.56 k
W
0 V to REF
VIN
Note 3
NOTES
1Typical analog input impedance.
2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3
For this range the input is high impedance.
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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