參數(shù)資料
型號(hào): EVAL-AD7652CBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 17/28頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7652
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: 0 ~ 2.5 V
在以下條件下的電源(標(biāo)準(zhǔn)): 65mW @ 500kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7652
已供物品:
相關(guān)產(chǎn)品: AD7652ASTZ-ND - IC ADC 16BIT 500KSPS REF 48LQFP
AD7652ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP
AD7652
MICROPROCESSOR INTERFACING
The AD7652 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7652 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7652 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7652 with an ADSP-219x SPI equipped DSP.
SPI Interface (ADSP-219x)
Figure 37. Interfacing the AD7652 to an SPI Interface
shows an interface diagram between the AD7652 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7652 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY
going LOW) using an interrupt line of the DSP. The serial inter-
face (SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps, which
allows it to read an ADC result in less than 1 s. When a higher
sampling rate is desired, use of one of the parallel interface
modes is recommended.
AD7652*
ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
* ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
02965-0-021
Rev. 0 | Page 24 of 28
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