參數(shù)資料
型號: EVAL-AD7652CBZ
廠商: Analog Devices Inc
文件頁數(shù): 15/28頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7652
標準包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: 0 ~ 2.5 V
在以下條件下的電源(標準): 65mW @ 500kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7652
已供物品:
相關產(chǎn)品: AD7652ASTZ-ND - IC ADC 16BIT 500KSPS REF 48LQFP
AD7652ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7652ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP
AD7652
SLAVE SERIAL INTERFACE
External Clock
The AD7652 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS. When CS and RD
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F
and F
show the detailed timing
diagrams of these methods.
Figure 34. Slave Serial Data Timing for Reading (Read after Convert)
Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
While the AD7652 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7652 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during the
latter half of BUSY HIGH.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
X15
X14
X
1
2
3
14
151617
18
t34
02964-0-017
EXT/INT = 1
RD
RD = 0
SDOUT
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
t3
t35
t36 t37
t31
t32
t16
BUSY
EXT/INT = 1
INVSCLK = 0
02965-0-018
CNVST
CS
RD = 0
Rev. 0 | Page 22 of 28
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