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| 型號： | EVAL-AD7608EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7608 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI? |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 100mW @ 200kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7608 |
| 已供物品： | 板 |
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AD7608
Data Sheet
Rev. A | Page 24 of 32
DIGITAL INTERFACE
The AD7608 provides two interface options: a parallel interface
and high speed serial interface. The required interface mode is
selected via the
AA
PAREE
AA
/SER SEL pin.
The operation of the interface modes is discussed in the
following sections.
PARALLEL INTERFACE (PAR/SER SEL = 0)
Data can be read from the AD7608 via the parallel data bus with
standard
AA
CSEE
AA
and
AA
RDEE
AA
signals. To read the data over the parallel
bus, the
AA
PAREE
AA
/SER SEL pin should be tied low. The
AA
CSEE
AA
and
AA
RDEE
AA
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both
AA
CSEE
AA
and
AA
RDEE
AA
are logic low.
AD7608
14
BUSY
12
RD/SCLK
[33:24]
[22:16]
DB[15:0]
13
CS
DIGITAL
HOST
INTERRUPT
08938-
040
Figure 42. AD7608 interface diagram—One AD7608 Using the Parallel Bus;
AA
CSEE
AA
and
AA
RDEE
AA
Shorted Together
The rising edge of the
AA
CSEE
AA
input signal three-states the bus
and the falling edge of the
AA
CSEE
AA
input signal takes the bus out
of the high impedance state.
AA
CSEE
AA
is the control signal that
enables the data lines, it is the function that allows multiple
AD7608 devices to share the same parallel data bus.
The
AA
CSEE
AA
signal can be permanently tied low, and the
AA
RDEE
AA
signal can be used to access the conversion results as shown
in Figure 4. A read operation of new data can take place after
the BUSY signal goes low (Figure 2), or alternatively a read
operation of data from the previous conversion process can
take place while BUSY is high (Figure 3).
The
AA
RDEE
AA
pin is used to read data from the output conversion
results register. Two
AA
RDEE
AA
pulses are required to read the full
18-bit conversion result from each channel. Applying a sequence
of 16
AA
RDEE
AA
pulses to the AD7608
AA
RDEE
AA
pin clocks the conversion
results out from each channel onto the 16-bit parallel output
bus in ascending order. The first
AA
RDEE
AA
falling edge after BUSY
goes low clocks out DB[17:2] of the V1 result, the next
AA
RDEE
AA
falling edge updates the bus with DB[1:0] of V1 result. It takes
16
AA
RDEE
AA
pulses to read the eight 18-bit conversion results from
the AD7608. On the AD7608, the 16th falling edge of
AA
RDEE
AA
clocks
out the DB[1:0] conversion result for Channel V8. When the
AA
RDEE
AA
signal is logic low, it enables the data conversion result from
each channel to be transferred to the digital host (DSP, FPGA).
When there is only one AD7608 in a system/board and it does
not share the parallel bus, data can be read using just one control
signal from the digital host. The
AA
CSEE
AA
and
AA
RDEE
AA
signals can be tied
together as shown in Figure 5. In this case, the data bus comes
out of three-state on the falling edge of
AA
CSEE
AA
/
AA
RDEE
AA
. The combined
AA
CSEE
AA
and
AA
RDEE
AA
signal allows the data to be clocked out of the AD7608
and to be read by the digital host. In this case,
AA
CSEE
AA
is used to
frame the data transfer of each data channel. In this case, 16
AA
CSEE
AA
pulses are required to read the eight channels of data.
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