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參數資料
| 型號： | EVAL-AD7376EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7376 |
| 標準包裝： | 1 |
| 主要目的： | 數字電位器 |
| 已用 IC / 零件： | AD7376 |
| 已供物品： | 板 |
| 相關產品： | AD7376ARUZ10-ND - IC DGTL POT 128POS 10K 14TSSOP AD7376ARUZ10-R7DKR-ND - IC DIGITAL POT 10K 14-TSSOP AD7376ARWZ10-RL-ND - IC POT DIGITAL 10K 16-SOIC AD7376ARUZ100-R7DKR-ND - IC POT DIGITAL 128POS 14-TSSOP AD7376ARUZ100-R7CT-ND - IC POT DIGITAL 128POS 14-TSSOP AD7376ARUZ100-R7TR-ND - IC POT DIGITAL 128POS 14-TSSOP AD7376ARUZ100-ND - IC POT DIGITAL 128POS 14-TSSOP AD7376ARWZ50-ND - IC DIGITAL POT 50K 16-SOIC AD7376ARWZ100-ND - IC DIGITAL POT 100K 16-SOIC AD7376ARWZ10-ND - IC POT DIGITAL 10K 16-SOIC 更多... |
AD7376
Rev. D | Page 13 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A that is
proportional to the input voltage at Terminal A to Terminal B.
Unlike the polarity of VDD to GND, which must be positive,
voltage across Terminal A to Terminal B, Wiper W to Terminal A,
and Wiper W to Terminal B can be at either polarity.
A
VI
W
B
VO
0
11
19-
026
Figure 26. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for the purpose of
approximation, connecting the Terminal A to 30 V and the
Terminal B to ground produces an output voltage at the Wiper W
to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each
LSB of voltage is equal to the voltage applied across Terminals A
and B divided by the 128 positions of the potentiometer divider.
The general equation defining the output voltage at VW with
respect to ground for any valid input voltage applied to
Terminals A and B is
A
W
V
D
V
128
)
(
=
(3)
A more accurate calculation that includes the effect of wiper
resistance, VW
, is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
when in rheostat mode, the output voltage in divider mode is
primarily dependent on the ratio, not the absolute values, of the
internal resistors RWA and RWB. Therefore, the temperature drift
reduces to 5 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD7376 contains a 3-wire digital interface (CS, CLK, and
SDI). The 7-bit serial word must be loaded MSB first. The
format of the word is shown in Figure 2. The positive edge-
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic
families work well. When CS is low, the clock loads data into the
serial register upon each positive clock edge.
The data setup and hold times in Table 3 determine the valid
timing requirements. The AD7376 uses a 7-bit serial input data
register word that is transferred to the internal RDAC register
when the CS line returns to logic high. Extra MSB bits are
ignored.
The AD7376 powers up at a random setting. However, the
midscale preset or any desirable preset can be achieved by
manipulating RS or SHDN with an extra I/O.
When the reset (RS) pin is asserted, the wiper resets to the
midscale value. Midscale reset can be achieved dynamically or
during power-up if an extra I/O is used.
When the SHDN pin is asserted, the AD7376 opens SWA to let
the Terminal A float and to short Wiper W to Terminal B. The
AD7376 consumes negligible power during the shutdown mode
and resumes the previous setting once the SHDN pin is released.
On the other hand, the AD7376 can be programmed with any
settings during shutdown. With an extra programmable I/O
asserting shutdown during power-up, this unique feature allows
the AD7376 with programmable preset at any desirable level.
Table 7 shows the logic truth table for all operations.
Table 7. Input Logic Control Truth Table1
CLK
CS
RS
SHDN
Register Activity
L
H
Enables SR, enables SDO pin.
P
L
H
Shifts one bit in from the SDI pin. The
seventh previously entered bit is
shifted out of the SDO pin.
X
P
H
Loads SR data into 7-bit RDAC latch.
X
H
No operation.
X
L
H
Sets 7-bit RDAC latch to midscale,
wiper centered, and SDO latch cleared.
X
H
P
H
Latches 7-bit RDAC latch to 0x40.
X
H
L
Opens circuits resistor of Terminal A,
connects Wiper W to Terminal B,
turns off SDO output transistor.
1
P = positive edge, X = don’t care, and SR = shift register.
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