參數(shù)資料
型號(hào)： EVAL-AD7324CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/37頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7324CBZ
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 30mW @ 1MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7324
已供物品： 板
相關(guān)產(chǎn)品： AD7324BRUZ-REEL-ND - IC ADC 12BIT+SAR 4CHAN 16-TSSOP
AD7324BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
AD7324BRUZ-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
Data Sheet
AD7324
Rev. B | Page 33 of 36
APPLICATION HINTS
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7324 should be
designed so that the analog and digital sections are confined to
certain areas of the board. This design facilitates the use of ground
planes that can easily be separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins on the AD7324
should be connected to the AGND plane. Digital and analog
ground pins should be joined in only one place. If the AD7324
is in a system where multiple devices require an AGND and
DGND connection, the connection should still be made at only
one point. A star point should be established as close as possible
to the ground pins on the AD7324.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7324 device because
this couples noise onto the die. However, the analog ground
plane should be allowed to run under the AD7324 to avoid
noise coupling. The power supply lines to the AD7324 device
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board, compo-
nents, such as clocks, with fast switching signals should be shielded
with digital ground and never run near the analog inputs. Avoid
crossover of digital and analog signals. To reduce the effects of
feedthrough within the board, traces should be run at right angles
to each other. A microstrip technique is the best method, but
its use may not be possible with a double-sided board. In this
technique, the component side of the board is dedicated to ground
planes, and signals are placed on the other side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 F tantalum capacitors in parallel with
0.1 F capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 F capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is
typical of common ceramic and surface mount types of
capacitors. These low ESR, low ESI capacitors provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
POWER SUPPLY CONFIGURATION
It is recommended that Schottky diodes be placed in series with
the AD7324 VDD and VSS supply signals. Figure 54 shows this
Schottky diode configuration. BAT43 Schottky diodes are used.
1ADDITIONAL PINS OMITTED FOR CLARITY. 04864-
056
AD73241
V+
V–
3V/5V
VSS
VDD
VCC
SCLK
VIN0
DIN
VIN2
DOUT
VIN3
VIN1
CS
Figure 54. Schottky Diode Connection
In an application where non-symmetrical VDD and VSS supplies
are being used, adhere to the following guidelines. Table 16
outlines the VSS supply range that can be used for particular VDD
voltages when non-symmetrical supplies are required. When
operating the AD7324 with low VDD and VSS voltages, it is
recommended that these supplies be symmetrical.
Table 16. Non-Symmetrical VDD and VSS Requirements
VDD
Typical VSS Range
5 V
5 V to 5.5 V
6 V
5 V to 8.5 V
7 V
5 V to 11.5 V
8 V
5 V to 15 V
9 V
5 V to 16.5 V
10 V to 16.5 V
5 V to 16.5 V
For the 0 to 4 × VREF range, VSS can be tied to AGND as per
minimum supply recommendations outlined in Table 6.
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