參數(shù)資料
型號(hào)： EVAL-AD7324CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 13/37頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7324CBZ
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 30mW @ 1MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7324
已供物品： 板
相關(guān)產(chǎn)品： AD7324BRUZ-REEL-ND - IC ADC 12BIT+SAR 4CHAN 16-TSSOP
AD7324BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
AD7324BRUZ-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
Data Sheet
AD7324
Rev. B | Page 19 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7324.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7324 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7324 can operate
with either an internal or external reference. In Figure 32, the
AD7324 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The VCC pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. The VDD and VSS are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The VDRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the VDRIVE input controls the voltage of
the serial interface. VDRIVE can be set to 3 V or 5 V.
AD7324
VCC
VDD1
SERIAL
INTERFACE
C/P
VIN0
VIN1
VIN2
VIN3
REFIN/OUT
CS
DOUT
VDRIVE
SCLK
DIN
DGND
10F
0.1F
+
10F
0.1F
+
10F
0.1F
+
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
+15V
–15V
680nF
VSS1
VCC +2.7V TO +5.25V
1MINIMUM VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
10F
0.1F
+
+3V SUPPLY
0
4864
-02
5
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7324 has a total of four analog inputs when operating in
single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7324 in single-
ended mode.
AD73241
VIN+
V+
V–
VDD
VSS
VCC
5V
AGND
1ADDITIONAL PINS OMITTED FOR CLARITY.
0
4864-
026
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7324 can have a total of two true differential analog
input pairs. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
common-mode rejection of the device and improvements in
distortion performance. Figure 34 defines the configuration of
the true differential analog inputs of the AD7324.
AD73241
VIN+
VIN–
1ADDITIONAL PINS OMITTED FOR CLARITY.
04864-
02
7
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN pins in
each differential pair (VIN+ VIN). VIN+ and VIN should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × VREF mode, the amplitude of the
differential signal is 20 V to +20 V p-p (2 × 4 × VREF),
regardless of the common mode.
The common mode is the average of the two signals
(VIN+ + VIN)/2
and is, therefore, the voltage on which the two input signals
are centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common mode range is
determined by the output swing of the amplifier. If the
differential inputs are not driven from an amplifier, the
common-mode range is determined by the supply voltage on
the VDD supply pin and the VSS supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude 2 × (4 × VREF) to +2 ×
(4 × VREF) corresponding to digital Code 4096 to Code +4095.
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