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參數(shù)資料
| 型號： | EVAL-AD7191EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7191 |
| 設(shè)計資源： | EVAL-AD7191 Schematic AD7191 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±5 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7191 |
| 已供物品： | 板 |
AD7191
Rev. A | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
12
11
MCLK2
SCLK
PDOWN
PGA1
PGA2
CLKSEL
MCLK1
CHAN
TEMP
AIN2
AIN1
NC
20
21
22
23
24
19
18
17
16
15
14
13
DOUT/RDY
ODR1
DVDD
AGND
DGND
AVDD
BPDSW
REFIN(–)
AIN3
AIN4
REFIN(+)
ODR2
AD7191
TOP VIEW
(Not to Scale)
08
16
3-
0
04
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
MCLK1
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2. Alternatively, the MCLK1 pin can be driven with a CMOS-compatible clock and MCLK2
left unconnected.
2
MCLK2
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
3
SCLK
Serial Clock Input. This serial clock input is for controlling data transfers from the ADC. The SCLK has a
Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can
be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a non-
continuous clock with the information transmitted to or from the ADC in smaller batches of data.
4
PDOWN
Power-Down Pin, Digital Input. The PDOWN pin functions as a power-down pin and a reset pin. When
PDOWN is taken high, the AD7191 is powered down and the DOUT/RDY pin is tristated. The circuitry and
serial interface are also reset. This resets the logic, the digital filter, and the analog modulator. PDOWN
must be held high for 100 ns minimum to initiate the reset function.
5
CLKSEL
Clock Select, Digital Input Pin. This pin selects the clock source to be used by the AD7191. When CLKSEL is
tied low, the external clock/crystal is used as the clock source. When CLKSEL is tied high, the internal
4.92 MHz clock is used as the clock source to the AD7191.
6
PGA2
Gain Select, Digital Input Pin. This pin is used in conjunction with PGA1 to set the gain. See Table 7.
7
PGA1
Gain Select, Digital Input Pin. This pin is used in conjunction with PGA2 to set the gain. See Table 7.
8
CHAN
Channel Select, Digital Input Pin. This pin is used to select the channel.
When CHAN is tied low, channel AIN1/AIN2 is selected.
When CHAN is tied high, channel AIN3/AIN4 is selected.
9
TEMP
Temperature Sensor Select, Digital Input Pin. The internal temperature sensor is selected when TEMP is
tied high. When TEMP is tied low, the analog input channel AIN1/AIN2 or AIN3/AIN4 is the selected
channel (as determined by the CHAN pin).
10
NC
No Connect. This pin should be tied to AGND.
11
AIN1
Analog Input. AIN1 is the positive input of the fully differential input pair AIN1/AIN2.
12
AIN2
Analog Input. AIN2 is the negative input of the fully differential input pair AIN1/AIN2.
13
AIN3
Analog Input. AIN3 is the positive input of the fully differential input pair AIN3/AIN4.
14
AIN4
Analog Input. AIN
4 is the negative input of the fully differential input pair AIN3/AIN4.
15
REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(). REFIN(+)
can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN(+) REFIN()), is
AVDD, but the part functions with a reference from 1 V to AVDD.
16
REFIN()
Negative Reference Input. This reference input can lie anywhere between AGND and AVDD 1 V.
17
BPDSW
Bridge Power-Down Switch to AGND. When PDOWN is low, the bridge power-down switch is closed.
When PDOWN is high, the bridge power-down switch is opened.
18
AGND
Analog Ground Reference Point.
19
DGND
Digital Ground Reference Point.
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