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參數(shù)資料
| 型號(hào)： | EVAL-AD7191EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7191 |
| 設(shè)計(jì)資源： | EVAL-AD7191 Schematic AD7191 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±5 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7191 |
| 已供物品： | 板 |
AD7191
Rev. A | Page 6 of 20
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter1, 2
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
Read Operation
t1
0
ns min
PDOWN falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after PDOWN inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to PDOWN inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the ADC. The digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V,
100A WITH DVDD = 3V)
ISOURCE (200A WITH DVDD = 5V,
100A WITH DVDD = 3V)
1.6V
TO
OUTPUT
PIN
50pF
08
16
3-
00
2
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAM
t1
t3
t2
t7
t6
t5
t4
PDOWN (I)
NOTES
1. I = INPUT, O = OUTPUT
DOUT/RDY (O)
SCLK (I)
08
16
3-
00
3
Figure 3. Read Cycle Timing Diagram
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| EVAL-AD7192EBZ | 功能描述:BOARD EVAL FOR AD7192 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7192EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD7192 24BIT ADC |
| EVAL-AD7193EBZ | 功能描述:EVAL BOARD FOR AD7193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7194EBZ | 功能描述:EVAL BOARD FOR AD7194 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7195EBZ | 功能描述:BOARD EVAL FOR AD7195 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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