All input signals are specified with tr = tf = 5 ns (10% to 90% of V
參數(shù)資料
型號(hào): EVAL-AD5930EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5930
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),波形發(fā)生器
已用 IC / 零件: AD5930
次要屬性: 串行接口
已供物品: 板,線纜
AD5930
Data Sheet
Rev. | Page 6 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.1
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
20
ns min
MCLK period
t2
8
ns min
MCLK high duration
t3
8
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high time
t6
10
ns min
SCLK low time
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8
10
ns min
FSYNC to SCLK hold time
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
2 x t1
ns min
Minimum CTRL pulse width
t12
0
ns min
CTRL rising edge to MCLK falling edge setup time
t13
10 x t1
ns typ
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
8 x t1
ns typ
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
t14
2 x t1
ns typ
Frequency change to SYNC output, saw sweep, each frequency increment
t15
2 x t1
ns typ
Frequency change to SYNC output, saw sweep, end of sweep
t16
2 x t1
ns typ
Frequency change to SYNC output, triangle sweep, end of sweep
t17
20
ns max
MCLK falling edge after 16th clock edge to MSB out
1
Guaranteed by design, not production tested.
MCLK
t3
t2
t1
05333-
003
Figure 3. Master Clock
SCLK
FSYNC
SDATA
D15
D14
D2
D1
D0
D15
D14
t7
t9
t6
t8
t10
t5
t4
05333-
004
Figure 4. Serial Timing
B
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