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| 型號： | EVAL-AD5755SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 5/52頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5755 |
| 視頻文件： | AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC |
| 標準包裝： | 1 |
| DAC 的數量： | 4 |
| 位數： | 16 |
| 數據接口： | 串行 |
| 設置時間： | 11µs |
| DAC 型： | 電流/電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5755 |
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Data Sheet
AD5755
Rev. C | Page 13 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PO
C
R
ESET
AV
DD
CO
M
P
L
V_
A
–V
SEN
SE_
A
+V
SEN
SE_
A
CO
M
P
DCDC_
A
V
B
OOS
T
_
A
V
O
UT
_
A
I O
UT
_
A
AV
SS
CO
M
P
L
V_
B
–V
SEN
SE_
B
+V
SEN
SE_
B
V
O
UT
_
B
CO
M
P
DCDC_
B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R
SET
_
C
R
SET
_
D
RE
F
O
UT
R
E
FIN
CO
M
P
L
V_
D
–V
SEN
SE_
D
+V
SEN
SE_
D
CO
M
P
DCDC_
D
V
B
OOS
T
_
D
V
O
UT
_
D
I O
UT
_
D
AV
SS
CO
M
P
L
V_
C
–V
SEN
SE_
C
+V
SEN
SE_
C
V
O
UT
_
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RSET_B
RSET_A
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
CLEAR
ALERT
FAULT
COMPDCDC_C
IOUT_C
VBOOST_C
AVCC
SWC
GNDSWC
GNDSWD
SWD
AVSS
SWA
GNDSWA
GNDSWB
SWB
AGND
VBOOST_B
IOUT_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5755
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. THIS EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIALOF THE
AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
07304-
006
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RSET_B
An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_B
temperature drift performance. See the Device Features section.
2
RSET_A
An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_A
temperature drift performance. See the Device Features section.
3
REFGND
Ground Reference Point for Internal Reference.
4
REFGND
Ground Reference Point for Internal Reference.
5
AD0
Address Decode for the Device Under Test (DUT) on the Board.
6
AD1
Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC,
see the Packet Error Checking section.
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
SDO
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5.
11
DVDD
Digital Supply. The voltage range is from 2.7 V to 5.5 V.
12
DGND
Digital Ground.
13
LDAC
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The
LDAC pin must not be left unconnected.
14
CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more
information. When CLEAR is active, the DAC output register cannot be written to.
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